Other Parts Discussed in Thread: C2000WARE
#include "main.h"
float AdcIgrid[3] = {0};
float AdcVgrid[3] = {0};
float AdcItrack[3] = {0};
float AdcVdc = 0;
float AdcResults[12]={0};
float TEMPResults[4]={0};
float receivedV_CMD = 0.0f;
uint16_t modbus485_flag = 0;
uint16_t scictr = 0;
uint16_t check_Vdctime;
void main(void)
{
InitSysCtrl();//sysclk = 200MHz
DINT;
InitPieCtrl();
IER = 0x0000; //Disable CPU interrupts
IFR = 0x0000; //clear all CPU interrupt flags
InitPieVectTable();
ConfigPie();
InitCpuTimers();
ConfigCpuTimer(&CpuTimer0, 200, 20000);//20ms freq:200Mhz period:50us
ConfigCpuTimer(&CpuTimer1, 200, 2000);//2ms
ConfigCpuTimer(&CpuTimer2, 200, 20000);//20ms
ConfigGpio();
ConfigAdc();
ConfigEpwm();
// ConfigSci();
ConfigSciModbus();
ConfigCAN();
//user init function
StateUpdate_GlobalParaInit(); //disable epwm,safe restart set,set to idle state
Init_Sample_Para(); //sample flag,counter,realvalue initial
Init_Protection_Para();
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
//StartCpuTimer0();
StartCpuTimer1();
StartCpuTimer2();
while (1)
{
ScanKey();
LightBeepCMD();
// CAN_SendSystemState(Sys_Current_State);
// CAN_SendCurrentData(Sample_CalcResult.Itrack_Ave);
// ���Դ���
static uint32_t counter = 0;
if(counter++ % 100 == 0) { // ÿ100��ѭ������һ��
uint16_t testData[2] = {0xAA55, counter};
GpioDataRegs.GPCTOGGLE.bit.GPIO89 = 1; // ����ָʾ��
CAN_SendData(16, 0x123, testData, 2);
GpioDataRegs.GPCTOGGLE.bit.GPIO89 = 1; // ����ָʾ��
}
if (modbus485_flag == 1)
{
modbus485_flag = 0;
Deal_Modbus485();
}
}
}
void ConfigPie(void)//�����
{
EALLOW;
PieVectTable.TIMER0_INT = &CpuTimer0_ISR;
PieVectTable.TIMER1_INT = &CpuTimer1_2ms_ISR;
PieVectTable.TIMER2_INT = &CpuTimer2_20ms_ISR;
PieVectTable.ADCD1_INT = &Adcd_ISR;
PieVectTable.SCIA_RX_INT = &SciaModbusRxFifo_ISR;
PieVectTable.CANA0_INT = &CAN_ISR;
EDIS;
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;//cputimer0
PieCtrlRegs.PIEIER1.bit.INTx6 = 1;//adcd
PieCtrlRegs.PIEIER9.bit.INTx3 = 1;//scia rx
PieCtrlRegs.PIEIER9.bit.INTx1 = 1;//can int
IER |= M_INT1;//cputimer0 adcd
IER |= M_INT13;//cputimer1
IER |= M_INT14;//cputimer2
IER |= M_INT9;//scia rx
}
void ConfigGpio(void)
{
EALLOW;
//output
//led88
GpioCtrlRegs.GPCPUD.bit.GPIO88 = 1; //PUD DISl:1��ENABLE:0
GpioCtrlRegs.GPCDIR.bit.GPIO88 = 1; //1:OUT;0:IN
GpioCtrlRegs.GPCMUX2.bit.GPIO88 = 0; //GPIO
GpioDataRegs.GPCCLEAR.bit.GPIO88 = 1; //DATA CLEAR
//led89
GpioCtrlRegs.GPCPUD.bit.GPIO89 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO89 = 1;
GpioCtrlRegs.GPCMUX2.bit.GPIO89 = 0;
GpioDataRegs.GPCCLEAR.bit.GPIO89 = 1;
//led90
GpioCtrlRegs.GPCPUD.bit.GPIO90 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO90 = 1;
GpioCtrlRegs.GPCMUX2.bit.GPIO90 = 0;
GpioDataRegs.GPCCLEAR.bit.GPIO90 = 1;
//ACContactor_Ctrl
GpioCtrlRegs.GPBPUD.bit.GPIO44 = 1;
GpioCtrlRegs.GPBDIR.bit.GPIO44 = 1;
GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 0;
GpioDataRegs.GPBCLEAR.bit.GPIO44 = 1;
//fan ctrl
GpioCtrlRegs.GPBPUD.bit.GPIO63 = 1;
GpioCtrlRegs.GPBDIR.bit.GPIO63 = 1;
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 0;
GpioDataRegs.GPBCLEAR.bit.GPIO63 = 1;
//Light_Yellow
GpioCtrlRegs.GPCPUD.bit.GPIO64 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO64 = 1;
GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 0;
GpioDataRegs.GPCCLEAR.bit.GPIO64 = 1;
//Light_Green
GpioCtrlRegs.GPCPUD.bit.GPIO65 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1;
GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 0;
GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1;
//Light_Red
GpioCtrlRegs.GPCPUD.bit.GPIO66 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO66 = 1;
GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 0;
GpioDataRegs.GPCCLEAR.bit.GPIO66 = 1;
//IGBT
GpioCtrlRegs.GPBPUD.bit.GPIO60 = 1;
GpioCtrlRegs.GPBDIR.bit.GPIO60 = 1;
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 0;
GpioDataRegs.GPBCLEAR.bit.GPIO60 = 1;
//RELAY
GpioCtrlRegs.GPBPUD.bit.GPIO59 = 1;
GpioCtrlRegs.GPBDIR.bit.GPIO59 = 1;
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 0;
GpioDataRegs.GPBCLEAR.bit.GPIO59 = 1;
//����
GpioCtrlRegs.GPBPUD.bit.GPIO58 = 1;
GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1;
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0;
GpioDataRegs.GPBCLEAR.bit.GPIO58 = 1;
//TEMP0
GpioCtrlRegs.GPCPUD.bit.GPIO68 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1;
GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 0;
GpioDataRegs.GPCCLEAR.bit.GPIO68 = 1;
//TEMP1
GpioCtrlRegs.GPCPUD.bit.GPIO69 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1;
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 0;
GpioDataRegs.GPCCLEAR.bit.GPIO69 = 1;
//input
//key reset
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; //1:DISABLE;0:ENABLE
GpioCtrlRegs.GPADIR.bit.GPIO8 = 0; //1:OUT;0:IN
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; //0:GPIO
GpioDataRegs.GPACLEAR.bit.GPIO8 = 1; //1:CLEAR
//key start
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO9= 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0;
GpioDataRegs.GPACLEAR.bit.GPIO9 = 1;
//key stop
GpioCtrlRegs.GPDPUD.bit.GPIO99 = 1;
GpioCtrlRegs.GPDDIR.bit.GPIO99 = 0;
GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0;
GpioDataRegs.GPDCLEAR.bit.GPIO99 = 1;
//ac contactor return
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO5 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 0;
GpioDataRegs.GPACLEAR.bit.GPIO5 = 1;
// Track Temp check
GpioCtrlRegs.GPBPUD.bit.GPIO62 = 1;
GpioCtrlRegs.GPBDIR.bit.GPIO62 = 0;
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 0;
GpioDataRegs.GPBCLEAR.bit.GPIO62 = 1;
// IGBT check
GpioCtrlRegs.GPBPUD.bit.GPIO61 = 1;
GpioCtrlRegs.GPBDIR.bit.GPIO61 = 0;
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0;
GpioDataRegs.GPBCLEAR.bit.GPIO61 = 1;
//Itrack hardware protection signal from CPLD(PRO2)
GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 0;
GpioCtrlRegs.GPBDIR.bit.GPIO43 = 0; // gpio input
GpioCtrlRegs.GPBPUD.bit.GPIO43 = 1; //disable pull-up
GpioCtrlRegs.GPBQSEL1.bit.GPIO43 = 3; //async input mode
GpioDataRegs.GPBSET.bit.GPIO43 = 1;
//Vdc hardware protection signal from CPLD(PRO1)
GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 0;
GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0; // gpio input
GpioCtrlRegs.GPCPUD.bit.GPIO67 = 1; //disable pull-up
GpioCtrlRegs.GPCQSEL1.bit.GPIO67 = 3; //async input mode
GpioDataRegs.GPCDAT.bit.GPIO67 = 1;
//pro3
// GpioCtrlRegs.GPBPUD.bit.GPIO43 = 1;
// GpioCtrlRegs.GPBDIR.bit.GPIO43= 0;
// GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 0;
// GpioDataRegs.GPBCLEAR.bit.GPIO43=1;
//����GPIO
// GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1;
// GpioCtrlRegs.GPADIR.bit.GPIO22 = 1;
// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0;
// GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
EALLOW;
//config gpio87 for scib rx
GpioCtrlRegs.GPCPUD.bit.GPIO87 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO87 = 0;
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 0;
GpioDataRegs.GPCCLEAR.bit.GPIO87 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO87 = 0;
//config gpio86 for scib tx
GpioCtrlRegs.GPCPUD.bit.GPIO86 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO86 = 1;
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 0;
GpioDataRegs.GPCCLEAR.bit.GPIO86 = 1;
//config gpio86 for scib re
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1;
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1;//disable pull-up
GpioDataRegs.GPASET.bit.GPIO0 = 1; //zhujifasong
EDIS;
EALLOW;
//config gpio25 for MOSI send
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO25 = 1;
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0;
GpioDataRegs.GPACLEAR.bit.GPIO25 = 1;
//config gpio25 for MISO receive
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO22 = 0;
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0;
GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
// GpioDataRegs.GPADAT.bit.GPIO22 = 0;
//// config gpio70 for CAN TX
// GpioCtrlRegs.GPCPUD.bit.GPIO71 = 1;
// GpioCtrlRegs.GPCDIR.bit.GPIO71 = 0;
// GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 0;
// GpioDataRegs.GPCCLEAR.bit.GPIO71 = 1;
//
// //config gpio70 for CAN RX
// GpioCtrlRegs.GPCPUD.bit.GPIO70 = 1;
// GpioCtrlRegs.GPCDIR.bit.GPIO70 = 0;
// GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 0;
// GpioDataRegs.GPCCLEAR.bit.GPIO70 = 1;
EDIS;
EDIS;
}
#define TIMER_TBPRD 1250 // Period register
Uint32 CMPANUM = 625; // CMPA
Uint32 CMPBNUM = 470; // CMPB
Uint32 CMPANUMSCR = 0; // CMPA1
Uint32 CMPBNUMSCR = 0; // CMPB1
#define DB_DURATION 160 //160 3.2us//100*20ns=2us;D=48%
void ConfigEpwm(void)
{
#ifdef CODE_MASTER
EALLOW;
SyncSocRegs.SYNCSELECT.bit.SYNCOUT = 0x2; //select epwm7 sync signal to syncout
//config gpio24 for output xbar1
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1;//mux: output xbar1
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 1; //disable pull-up
GpioCtrlRegs.GPADIR.bit.GPIO24 = 1;//output
//config gpio25 for output xbar2
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1; //disable pull-up
GpioCtrlRegs.GPADIR.bit.GPIO25 = 1;//output
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1;//mux: output xbar2
//config output xbar1 for external sync out
OutputXbarRegs.OUTPUT1MUX0TO15CFG.bit.MUX14 = 0x3; //select external sync out
OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX14 = 0x1; //enable xbar mux
//config output xbar2 for external sync out
OutputXbarRegs.OUTPUT2MUX0TO15CFG.bit.MUX14 = 0x3; //select external sync out
OutputXbarRegs.OUTPUT2MUXENABLE.bit.MUX14 = 0x1; //enable xbar mux
EDIS;
#endif
#ifdef CODE_SLAVE
EALLOW;
//Config Gpio23 for syncin
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO23 = 0; // gpio input
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1; //disable pull-up
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; //sync input mode
//config input xbar5 to link gpio23 and EXTSYNCIN1
InputXbarRegs.INPUT5SELECT = 23;//select gpio 23
//select external sync for epwm7
SyncSocRegs.SYNCSELECT.bit.EPWM7SYNCIN = 0x5; //select EXTSYNCIN1
EDIS;
#endif
InitEPwm6Gpio(); //epwm.c,EPWM IO INIT ,100MHz by default
InitEPwm7Gpio();
InitEPwm8Gpio();
//pro3��disable TZ
EALLOW;
////Config Gpio42 PRO3 for ~TZ1
GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 0;
GpioCtrlRegs.GPBDIR.bit.GPIO42 = 0; // gpio input
GpioCtrlRegs.GPBPUD.bit.GPIO42 = 1; //disable pull-up
GpioCtrlRegs.GPBQSEL1.bit.GPIO42 = 2; //6 Samples Qualification
GpioCtrlRegs.GPBCTRL.bit.QUALPRD1 = 10; //qualification window = 2 * (PRD1 * 2) * 5ns * 5(Samples) = 1us
//input xbar
InputXbarRegs.INPUT1SELECT = 42;//select gpio 42
EDIS;
// //pro4
// EALLOW;
// //Config Gpio42 PRO3 for ~TZ1
// GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 0;
// GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0; // gpio input
// GpioCtrlRegs.GPBPUD.bit.GPIO47 = 1; //disable pull-up
// GpioCtrlRegs.GPBQSEL1.bit.GPIO47 = 3; //async input mode
// //input xbar
// InputXbarRegs.INPUT1SELECT = 47;//select gpio 47
// EDIS;
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;//turn off epwm clk,turn on after config
// Setup TBCLK
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count upDOWM
EPwm6Regs.TBPRD = TIMER_TBPRD; // Set timer period
EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm6Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm6Regs.TBCTR = 0x0000; // Clear counter
EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV2; //tbclk = 100M / 2 = 50M
// EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count upDOWM
EPwm7Regs.TBPRD = TIMER_TBPRD; // Set timer period
#ifdef CODE_MASTER
EPwm7Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
#endif
#ifdef CODE_SLAVE
EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading
EPwm7Regs.TBCTL.bit.PHSDIR = 1; //count up after sync
#endif
EPwm7Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm7Regs.TBCTR = 0x0000; // Clear counter
EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV2;
EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count upDOWM
EPwm8Regs.TBPRD = TIMER_TBPRD; // Set timer period
EPwm8Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading
EPwm8Regs.TBPHS.bit.TBPHS = 1180; // Phase is 170 , under initial condition
EPwm8Regs.TBCTL.bit.PHSDIR = 0; //count down after sync
EPwm8Regs.TBCTR = 0x0000; // Clear counter
EPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm8Regs.TBCTL.bit.CLKDIV = TB_DIV2;
// EPwm8Regs.TBCTL.bit.SYNCOSEL=TB_CTR_ZERO;
// Setup shadow register load on ZERO
EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm8Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm8Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm8Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm8Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set Compare values
//
EPwm6Regs.CMPA.bit.CMPA = CMPANUMSCR; // Set compare A value
EPwm6Regs.CMPB.bit.CMPB = CMPBNUMSCR; // Set Compare B value
EPwm7Regs.CMPA.bit.CMPA = CMPANUM; // Set compare A value
// EPwm7Regs.CMPC = 1180;// Phase is 170 , under initial condition
EPwm8Regs.CMPA.bit.CMPA = CMPANUM; // Set compare A value
EPwm8Regs.CMPB.bit.CMPB = CMPBNUM; // Set Compare B value
// Set actions
//EPWM6B:0-5V EPWM6A:0-20mA, choose one
EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM2A on Period
EPwm6Regs.AQCTLA.bit.CAD = AQ_SET; // Set PWM2A on event A,
// up count
EPwm6Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Clear PWM2B on Period
EPwm6Regs.AQCTLB.bit.CAD = AQ_SET; // Set PWM2B on event B,
EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM2A on Period
EPwm7Regs.AQCTLA.bit.CAD = AQ_SET; // Set PWM2B on event B,
EPwm8Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM2A on Period
EPwm8Regs.AQCTLA.bit.CAD = AQ_SET; // Set PWM2A on event A,
EPwm8Regs.AQCTLA.bit.CBD = AQ_SET; // Set PWM2A on event A,
// Active Low complementary PWMs - setup the deadband
// EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
// EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
// EPwm6Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
// EPwm6Regs.DBRED.bit.DBRED = DB_DURATION;
// EPwm6Regs.DBFED.bit.DBFED = DB_DURATION;
EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL; //A:UP EDGE;B:FALL EDGE DBA_RED_DBB_FED
EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //11:TOTAL ENABLE;00:DISABLE
EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; //10:only B invert
EPwm7Regs.DBRED.bit.DBRED = DB_DURATION; //UP DELAY
EPwm7Regs.DBFED.bit.DBFED = DB_DURATION; //FALL DELAY
EPwm8Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm8Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm8Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm8Regs.DBRED.bit.DBRED = DB_DURATION;
EPwm8Regs.DBFED.bit.DBFED = DB_DURATION;
EPwm8Regs.DBCTL.bit.OUTSWAP = 3;
//ADC trig setting
EPwm7Regs.ETSEL.bit.SOCASEL = ET_CTR_PRDZERO; //SOC event choose
EPwm7Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm7Regs.ETPS.bit.SOCAPRD = 1; //1-3times trig ADC
// EPwm7Regs.ETSEL.bit.SOCBSEL = ET_CTR_PRDZERO;
// EPwm7Regs.ETSEL.bit.SOCBEN = 1;
// EPwm7Regs.ETPS.bit.SOCBPRD = 1;
//TZ SETTING
//EPwm6Regs.TZSEL.bit.CBC1 = 1;//select TZ1 cbc
EPwm6Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm6Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
//EPwm6Regs.TZCLR.bit.CBCPULSE = 0; //cbc clear when CTR = 0
//EPwm6Regs.TZCLR.bit.OST = 1;
EPwm6Regs.TZFRC.bit.OST = 1; //force oneshot TZ at start
EPwm7Regs.TZSEL.bit.CBC1 = 1;//select TZ1 cbc
EPwm7Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm7Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EPwm7Regs.TZCLR.bit.CBCPULSE = 0; //cbc clear when CTR = 0
//EPwm7Regs.TZCLR.bit.OST = 1;
EPwm7Regs.TZFRC.bit.OST = 1;
EPwm8Regs.TZSEL.bit.CBC1 = 1;//select TZ1 cbc
EPwm8Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm8Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EPwm8Regs.TZCLR.bit.CBCPULSE = 0; //cbc clear when CTR = 0
//EPwm8Regs.TZCLR.bit.OST = 1;
EPwm8Regs.TZFRC.bit.OST = 1;
EDIS;
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
}
void ConfigAdc(void)
{
EALLOW;
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to 200M/4=50M
AdcbRegs.ADCCTL2.bit.PRESCALE = 6;
AdccRegs.ADCCTL2.bit.PRESCALE = 6;
AdcdRegs.ADCCTL2.bit.PRESCALE = 6;
//12 bit single mode
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCD, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//Set pulse positions to late
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; //1:EOC convert�O0: AFTER SAMPLE
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//power up the ADC
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; //ADC power up
//delay for 1ms to allow ADC time to power up
DELAY_US(1000); //delay 1ms then power up
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
DELAY_US(1000);
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
DELAY_US(1000);
AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1;
DELAY_US(1000);
Uint16 acqps;
//
// Determine minimum acquisition window (in SYSCLKS) based on resolution
//
if(ADC_RESOLUTION_12BIT == AdcaRegs.ADCCTL2.bit.RESOLUTION)
{
acqps = 14; //75ns
}
else //resolution is 16-bit
{
acqps = 63; //320ns
}
//ADCINA0 VgridA
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0;
AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 17;
//ADCINB0 VgridC
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0;
AdcbRegs.ADCSOC0CTL.bit.ACQPS = acqps;
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 17;
//ADCINC2 IgridA
AdccRegs.ADCSOC0CTL.bit.CHSEL = 2;
AdccRegs.ADCSOC0CTL.bit.ACQPS = acqps;
AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 17;
//ADCIND1 IHbridge
AdcdRegs.ADCSOC0CTL.bit.CHSEL = 1;
AdcdRegs.ADCSOC0CTL.bit.ACQPS = acqps;
AdcdRegs.ADCSOC0CTL.bit.TRIGSEL = 17;
//ADCINB2 VgridB
AdcbRegs.ADCSOC1CTL.bit.CHSEL = 2;
AdcbRegs.ADCSOC1CTL.bit.ACQPS = acqps;
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 17;
//ADCINC3 IgridB
AdccRegs.ADCSOC1CTL.bit.CHSEL = 3;
AdccRegs.ADCSOC1CTL.bit.ACQPS = acqps;
AdccRegs.ADCSOC1CTL.bit.TRIGSEL = 17;
//ADCIND2 Itrack
AdcdRegs.ADCSOC1CTL.bit.CHSEL = 2;
AdcdRegs.ADCSOC1CTL.bit.ACQPS = acqps;
AdcdRegs.ADCSOC1CTL.bit.TRIGSEL = 17;
//ADCINB3 Vdc
AdcbRegs.ADCSOC2CTL.bit.CHSEL = 3;
AdcbRegs.ADCSOC2CTL.bit.ACQPS = acqps;
AdcbRegs.ADCSOC2CTL.bit.TRIGSEL = 17;
//ADCINC4 IgridC
AdccRegs.ADCSOC2CTL.bit.CHSEL = 4; //SOC0 will convert pin C4
AdccRegs.ADCSOC2CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC2CTL.bit.TRIGSEL = 17; //trigger on ePWM7 SOCA/C
//ADCIND3 Itrack
AdcdRegs.ADCSOC2CTL.bit.CHSEL = 3;
AdcdRegs.ADCSOC2CTL.bit.ACQPS = acqps;
AdcdRegs.ADCSOC2CTL.bit.TRIGSEL = 17;
//ADCIN15 Vref
AdcaRegs.ADCSOC15CTL.bit.CHSEL = 15;
AdcaRegs.ADCSOC15CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC15CTL.bit.TRIGSEL = 17;
//ADCIND4 TempIGBT
AdcdRegs.ADCSOC3CTL.bit.CHSEL = 4;
AdcdRegs.ADCSOC3CTL.bit.ACQPS = acqps;
AdcdRegs.ADCSOC3CTL.bit.TRIGSEL = 17;
//TEMP ���
AdcdRegs.ADCSOC0CTL.bit.CHSEL = 0;
AdcdRegs.ADCSOC0CTL.bit.ACQPS = acqps;
AdcdRegs.ADCSOC0CTL.bit.TRIGSEL = 17;
//ADC interrupt
AdcdRegs.ADCINTSEL1N2.bit.INT1SEL = 3; //end of SOC3 will set INT1 flag
AdcdRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcdRegs.ADCINTFLGCLR.bit.ADCINT1 = 17; //make sure INT1 flag is cleared
EDIS;
}
void ConfigSciModbus()
{
EALLOW;
//config gpio85 for scia rx
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 1;
GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 1;
GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3;//async input mode
GpioCtrlRegs.GPCPUD.bit.GPIO85 = 1;//disable pull-up
//config gpio84 for scia tx
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 1;
GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 1;
GpioCtrlRegs.GPCPUD.bit.GPIO84 = 1;//disable pull-up
//config gpio83 for scia re
GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 0;
GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
GpioCtrlRegs.GPCPUD.bit.GPIO83 = 1;//disable pull-up
GpioDataRegs.GPCCLEAR.bit.GPIO83 = 1;//clear gpio to rx
EDIS;
//low speed clk = sysclk/4 by default
EALLOW;
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 1;//low speed clk = sysclk/2 = 100M
EDIS;
//config scib
SciaRegs.SCICCR.bit.STOPBITS = 0; //1 stop bit
SciaRegs.SCICCR.bit.PARITY = 0; //0 for odd, 1 for even parity
SciaRegs.SCICCR.bit.PARITYENA = 0; //disable parity
SciaRegs.SCICCR.bit.LOOPBKENA = 0; //disable loop back
SciaRegs.SCICCR.bit.SCICHAR = 7; //8 data bit
SciaRegs.SCICTL1.bit.RXERRINTENA = 1; //disable rx err int
SciaRegs.SCICTL1.bit.SWRESET = 0; //reset sci, later need to re-enable by write 1 here
SciaRegs.SCICTL1.bit.SLEEP = 0; //disable sleep mode
SciaRegs.SCICTL1.bit.TXWAKE = 0; //no need to use tx feature for addr frame
SciaRegs.SCICTL1.bit.RXENA = 1; //enable rx
SciaRegs.SCICTL1.bit.TXENA = 1; // enable tx
SciaRegs.SCICTL2.bit.RXBKINTENA = 0; //disable rxbk int for both rxrdy and brkdt
SciaRegs.SCICTL2.bit.TXINTENA = 0; //disable tx int for txrdy
//config sci fifo
SciaRegs.SCIFFTX.bit.SCIRST = 1;//sci not reset
SciaRegs.SCIFFTX.bit.SCIFFENA = 1; //enable fifo
SciaRegs.SCIFFTX.bit.TXFIFORESET = 0;// reset tx fifo pointer and hold
SciaRegs.SCIFFTX.bit.TXFFINTCLR = 1; //clear the fifo int flag
SciaRegs.SCIFFTX.bit.TXFFIENA = 0; //disable fifo int
SciaRegs.SCIFFTX.bit.TXFFIL = 0;//fifo int level = 0
SciaRegs.SCIFFRX.bit.RXFFOVRCLR = 1;//clear fifo overflow flag
SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; //clear fifo int flag
SciaRegs.SCIFFRX.bit.RXFIFORESET = 0;// reset rx fifo pointer and hold
SciaRegs.SCIFFRX.bit.RXFFIENA = 1;//enable fifo int
SciaRegs.SCIFFRX.bit.RXFFIL = 8;//fifo int level = 0x11111 by default
//SCI Baud = LSPCLK / ((BRR + 1) *8) = 100M / ((1301 + 1) *8) = 38400.0 bps, BRR = 324
//4800 2603 0xa2b
//9600 515h
SciaRegs.SCIHBAUD.all = 0x5;
SciaRegs.SCILBAUD.all = 0x15;
SciaRegs.SCIFFTX.bit.TXFIFORESET = 1;// re-enable tx fifo
SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;// re-enable rx fifo
SciaRegs.SCICTL1.bit.SWRESET = 1;
}
void ConfigSci()
{
EALLOW;
//config gpio87 for scib rx
GpioCtrlRegs.GPCPUD.bit.GPIO87 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO87 = 0;
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 0;
GpioDataRegs.GPCCLEAR.bit.GPIO87 = 1;
//config gpio86 for scib tx
GpioCtrlRegs.GPCPUD.bit.GPIO86 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO86 = 1;
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 0;
GpioDataRegs.GPCCLEAR.bit.GPIO86 = 1;
//config gpio86 for scib re
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1;
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1;//disable pull-up
GpioDataRegs.GPASET.bit.GPIO0 = 1;
EDIS;
//low speed clk = sysclk/4 by default
EALLOW;
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 1;//low speed clk = sysclk/2 = 100M
EDIS;
//config scib
ScibRegs.SCICCR.bit.STOPBITS = 0; //1 stop bit
ScibRegs.SCICCR.bit.PARITY = 0; //0 for odd, 1 for even parity
ScibRegs.SCICCR.bit.PARITYENA = 0; //disable parity
ScibRegs.SCICCR.bit.LOOPBKENA = 0; //disable loop back
ScibRegs.SCICCR.bit.SCICHAR = 7; //8 data bit
ScibRegs.SCICTL1.bit.RXERRINTENA = 0; //disable rx err int
ScibRegs.SCICTL1.bit.SWRESET = 0; //reset sci, later need to re-enable by write 1 here
ScibRegs.SCICTL1.bit.SLEEP = 0; //disable sleep mode
ScibRegs.SCICTL1.bit.TXWAKE = 0; //no need to use tx feature for addr frame
ScibRegs.SCICTL1.bit.RXENA = 1; //enable rx
ScibRegs.SCICTL1.bit.TXENA = 1; // enable tx
ScibRegs.SCICTL2.bit.RXBKINTENA = 0; //disable rxbk int for both rxrdy and brkdt
ScibRegs.SCICTL2.bit.TXINTENA = 0; //disable tx int for txrdy
//config sci fifo
ScibRegs.SCIFFTX.bit.SCIRST = 1;//sci not reset
ScibRegs.SCIFFTX.bit.SCIFFENA = 1; //enable fifo
ScibRegs.SCIFFTX.bit.TXFIFORESET = 0;// reset tx fifo pointer and hold
ScibRegs.SCIFFTX.bit.TXFFINTCLR = 1; //clear the fifo int flag
ScibRegs.SCIFFTX.bit.TXFFIENA = 0; //disable fifo int
ScibRegs.SCIFFTX.bit.TXFFIL = 0;//fifo int level = 0
ScibRegs.SCIFFRX.bit.RXFFOVRCLR = 1;//clear fifo overflow flag
ScibRegs.SCIFFRX.bit.RXFFINTCLR = 1; //clear fifo int flag
ScibRegs.SCIFFRX.bit.RXFIFORESET = 0;// reset rx fifo pointer and hold
ScibRegs.SCIFFRX.bit.RXFFIENA = 0;//disable fifo int
ScibRegs.SCIFFRX.bit.RXFFIL = 4;//fifo int level = 0x11111 by default
//SCI Baud = LSPCLK / ((BRR + 1) *8) = 100M / ((1301 + 1) *8) = 38400.0 bps, BRR = 324
//4800 2603 0xa2b
ScibRegs.SCIHBAUD.all = 0xA;
ScibRegs.SCILBAUD.all = 0x2b;
ScibRegs.SCIFFTX.bit.TXFIFORESET = 1;// re-enable tx fifo
ScibRegs.SCIFFRX.bit.RXFIFORESET = 1;// re-enable rx fifo
ScibRegs.SCICTL1.bit.SWRESET = 1;
}
void Sci_SendByte(char a)
{
//set 485 RE
GpioDataRegs.GPASET.bit.GPIO0 = 1;
while (ScibRegs.SCIFFTX.bit.TXFFST != 0) {}
ScibRegs.SCITXBUF.bit.TXDT = a;
//ScibRegs.SCITXBUF.all = a;
}
void Sci_SendData2Vofa()
{
float scisysstate = (float)Sys_Current_State;
uint16_t* pResult = (uint16_t*)&(Sample_CalcResult.Itrack_Ave);//send sample calc value
uint16_t i = 0;
for (i = 0; i < 24; i++, pResult++)
{
Sci_SendByte(*pResult & 0xFF);
Sci_SendByte(*pResult >> 8);
}
pResult = (uint16_t*)&scisysstate;
for (i = 0; i < 2; i++, pResult++)//send sysstate
{
Sci_SendByte(*pResult & 0xFF);
Sci_SendByte(*pResult >> 8);
}
pResult = (uint16_t*)&Vdc_Ctrl_Filter.Out;
for (i = 0; i < 2; i++, pResult++)//send sysstate
{
Sci_SendByte(*pResult & 0xFF);
Sci_SendByte(*pResult >> 8);
}
pResult = (uint16_t*)&Vdc_Ctrl_PI.Error;
for (i = 0; i < 2; i++, pResult++)//send sysstate
{
Sci_SendByte(*pResult & 0xFF);
Sci_SendByte(*pResult >> 8);
}
pResult = (uint16_t*)&Vdc_Ctrl_PI.PI_Out;
for (i = 0; i < 2; i++, pResult++)//send sysstate
{
Sci_SendByte(*pResult & 0xFF);
Sci_SendByte(*pResult >> 8);
}
Sci_SendByte(0x00);
Sci_SendByte(0x00);
Sci_SendByte(0x80);
Sci_SendByte(0x7f);
}
//canͨ��
void ConfigCAN(void)
{
EALLOW;
// ����GPIO70����CAN RX
GpioCtrlRegs.GPCPUD.bit.GPIO70 = 1; // ��������
GpioCtrlRegs.GPCDIR.bit.GPIO70 = 0; // ����
GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // ����ΪCANRXA����
// ����GPIO71����CAN TX
GpioCtrlRegs.GPCPUD.bit.GPIO71 = 1; // ��������
GpioCtrlRegs.GPCDIR.bit.GPIO71 = 1; // ���
GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // ����ΪCANTXA����
EDIS;
EALLOW;
// ����CANʱ��
CpuSysRegs.PCLKCR10.bit.CAN_A = 1;
EDIS;
// �ȴ���������
while(CanaRegs.CAN_CTL.bit.Init != 1) {}
EALLOW;
// �����ʼ��ģʽ
CanaRegs.CAN_CTL.bit.Init = 1;
CanaRegs.CAN_CTL.bit.CCE = 1;
// ����CANλ��ʱ
// ����ϵͳʱ��100MHz��Ŀ�겨����1Mbps
// Tq = (BRP+1)/100MHz = 100ns (BRP=0)
// ͬ����=1Tq, ʱ���1=4Tq, ʱ���2=3Tq, ��ʱ��=8Tq
CanaRegs.CAN_BTR.bit.BRP = 19 ;
CanaRegs.CAN_BTR.bit.TSEG1 = 15;
CanaRegs.CAN_BTR.bit.TSEG2 = 2;
CanaRegs.CAN_BTR.bit.SJW = 1;
// �˳���ʼ��ģʽ
CanaRegs.CAN_CTL.bit.Init = 0;
CanaRegs.CAN_CTL.bit.CCE = 0;
EDIS;
// �ȴ���ʼ�����
while(CanaRegs.CAN_CTL.bit.Init == 1) {}
// ��ʼ����Ϣ����16���ڷ��͵�������
EALLOW;
CanaRegs.CAN_IF1CMD.bit.MSG_NUM = 16;
CanaRegs.CAN_IF1ARB.bit.ID = 0x101; // ��������ID
CanaRegs.CAN_IF1ARB.bit.Xtd = 0; // ��ID
CanaRegs.CAN_IF1ARB.bit.Dir = 0; // ���ͷ���
CanaRegs.CAN_IF1ARB.bit.MsgVal = 1; // ��Ϣ��Ч
CanaRegs.CAN_IF1MCTL.bit.DLC = 4; // ���ݳ���4�ֽ�
CanaRegs.CAN_IF1MCTL.bit.TxIE = 1; // ʹ�ܷ����ж�
EDIS;
// ��ʼ����Ϣ����17���ڷ���ϵͳ״̬
EALLOW;
CanaRegs.CAN_IF1CMD.bit.MSG_NUM = 17;
CanaRegs.CAN_IF1ARB.bit.ID = 0x102; // ϵͳ״̬ID
CanaRegs.CAN_IF1ARB.bit.Xtd = 0; // ��ID
CanaRegs.CAN_IF1ARB.bit.Dir = 0; // ���ͷ���
CanaRegs.CAN_IF1ARB.bit.MsgVal = 1; // ��Ϣ��Ч
CanaRegs.CAN_IF1MCTL.bit.DLC = 2; // ���ݳ���2�ֽ�
CanaRegs.CAN_IF1MCTL.bit.TxIE = 1; // ʹ�ܷ����ж�
EDIS;
EALLOW;
CanaRegs.CAN_IF2CMD.bit.MSG_NUM = 0; // ѡ������0
CanaRegs.CAN_IF2ARB.bit.ID = 0x123; // ���ý���ID
CanaRegs.CAN_IF2ARB.bit.Xtd = 0; // ��֡
CanaRegs.CAN_IF2ARB.bit.Dir = 1; // ���շ���
CanaRegs.CAN_IF2MCTL.bit.DLC = 4; // Ԥ�ڽ���4�ֽ�
CanaRegs.CAN_IF2MCTL.bit.RxIE = 1; // ʹ�ܽ����ж�
EDIS;
}
// ����ֱ����ѹ����
void CAN_SendData(uint16_t msgNum, uint32_t id, uint16_t* data, uint16_t length)
{
EALLOW;
// ������Ϣ����
CanaRegs.CAN_IF1CMD.bit.MSG_NUM = msgNum; // ѡ����Ϣ����
CanaRegs.CAN_IF1CMD.bit.DIR = 1; // д�뷽��
CanaRegs.CAN_IF1CMD.bit.Arb = 1; // �����ٲ���
CanaRegs.CAN_IF1CMD.bit.Control = 1; // ���¿�����
CanaRegs.CAN_IF1CMD.bit.DATA_A = 1; // ��������A��
CanaRegs.CAN_IF1CMD.bit.DATA_B = 1; // ��������B��
// ������ϢID������
CanaRegs.CAN_IF1ARB.bit.ID = id; // ������ϢID
CanaRegs.CAN_IF1ARB.bit.Xtd = 0; // ��ID
CanaRegs.CAN_IF1ARB.bit.Dir = 0; // ���ͷ���
CanaRegs.CAN_IF1ARB.bit.MsgVal = 1; // ��Ϣ��Ч
// �������ݳ���
CanaRegs.CAN_IF1MCTL.bit.DLC = length; // ���ݳ���
CanaRegs.CAN_IF1MCTL.bit.TxIE = 1; // ʹ�ܷ����ж�
// ��������
if(length > 0) CanaRegs.CAN_IF1DATA.all = *((uint32_t*)&data[0]);
if(length > 4) CanaRegs.CAN_IF1DATB.all = *((uint32_t*)&data[4]);
CanaRegs.CAN_IF1MCTL.bit.TxRqst = 1;
EDIS;
}
// ���͵�������
void CAN_SendCurrentData(float current)
{
uint16_t data[4];
*(float*)data = current;
CAN_SendData(16, 0x101, data, 4); // ʹ��ID 0x101���͵�������
}
// ����ϵͳ״̬
void CAN_SendSystemState(uint16_t state)
{
uint16_t data[2];
data[0] = state & 0xFF;
data[1] = (state >> 8) & 0xFF;
CAN_SendData(17, 0x102, data, 2); // ʹ��ID 0x102����ϵͳ״̬
}
// ����CAN����
interrupt void CAN_ISR(void)
{
// �����յ�����Ϣ
if (CanaRegs.CAN_IF2MCTL.bit.NewDat == 1) {
uint32_t id = CanaRegs.CAN_IF2ARB.bit.ID;
uint16_t length = CanaRegs.CAN_IF2MCTL.bit.DLC;
uint32_t dataLow = CanaRegs.CAN_IF2DATA.all;
uint32_t dataHigh = CanaRegs.CAN_IF2DATB.all;
// ����ID�����ͬ��Ϣ
switch(id) {
case 0x123: // ��ѹ����
receivedV_CMD = *(float*)&dataLow;
break;
// ������Ӹ�����Ϣ����
}
// ��������ݱ�־
CanaRegs.CAN_IF2MCTL.bit.NewDat = 0;
}
if(CanaRegs.CAN_ES.bit.BOff) {
// ���߹رջָ�����
CanaRegs.CAN_CTL.bit.Init = 1;
while(!CanaRegs.CAN_CTL.bit.Init);
CanaRegs.CAN_CTL.bit.Init = 0;
}
// ����жϱ�־
PieCtrlRegs.PIEACK.bit.ACK9 = 1;
}
void DisplayChartHEX(float *signal, Uint16 signal_num)
{
char i, temp2;
for(i=0; i<signal_num; i++)
{
temp2 = *((int32 *)&signal[i]);
Sci_SendByte(temp2);
temp2 = *((int32 *)&signal[i]) >> 8;
Sci_SendByte(temp2);
temp2 = *((int32 *)&signal[i]) >> 16;
Sci_SendByte(temp2);
temp2 = *((int32 *)&signal[i]) >> 24;
Sci_SendByte(temp2);
}
// Sci_SendByte(0x00);
// Sci_SendByte(0x00);
// Sci_SendByte(0x80);
// Sci_SendByte(0x7f);
}
void PWM_Enable(void)
{
EALLOW;
EPwm7Regs.TZCLR.bit.OST = 1;
EPwm8Regs.TZCLR.bit.OST = 1;
EDIS;
}
void PWM_Disable(void)
{
EALLOW;
EPwm7Regs.TZFRC.bit.OST = 1;
EPwm8Regs.TZFRC.bit.OST = 1;
EDIS;
}
void SCR_PWM_Enable(void)
{
EALLOW;
EPwm6Regs.TZCLR.bit.OST = 1;
EDIS;
}
void SCR_PWM_Disable(void)
{
EALLOW;
EPwm6Regs.TZFRC.bit.OST = 1;
EDIS;
}
void ScanKey(void)//run in while loop of main function
{
if(KeyStart_PinState == 1 || KeyReset_PinState == 1 || KeyStop_PinState == 1)
{
DELAY_US(8000); //delay 8ms
if(KeyStart_PinState == 1)
{
Peripheral_Switch_State.bit.Key_Start = 1;
}
if(KeyReset_PinState == 1)
{
Peripheral_Switch_State.bit.Key_Reset = 1;
}
if(KeyStop_PinState == 1)
{
Peripheral_Switch_State.bit.Key_Stop = 1;
}
}
else
{
Peripheral_Switch_State.byte.Byte2 = 0;
}
}
void Epwm78Test(void)
{
uint16_t temp;
static uint16_t dir = 1;
temp = EPwm8Regs.TBPHS.bit.TBPHS;
if(dir)
{
temp += 10;
}
else
{
temp -= 10;
}
if((temp > 1250) || (temp <= 0))
{
dir = !dir;
}
EPwm8Regs.TBPHS.bit.TBPHS = temp;
}
void KeyNRelayTest(void)
{
if (KeyStart_PinState)
{
AC_Contactor_On();
Light_Green_On();
}
else
{
AC_Contactor_Off();
Light_Green_Off();
}
if (KeyStop_PinState)
{
Light_Red_On();
}
else
{
Light_Red_Off();
}
if (KeyReset_PinState)
{
Light_Yellow_On();
}
else
{
Light_Yellow_Off();
}
if (ACContactor_ReturnState)
{
Fan_On();
}
else
{
Fan_Off();
}
}
//Uint32 TEMPSEL = 0; //TEMPSEL
//void TEMP_SEL(void)
//{
//// if(TEMPSEL == 0)
//// {
//// GpioDataRegs.GPCDAT.bit.GPIO68 = 1;
//// GpioDataRegs.GPCDAT.bit.GPIO69 = 1;
////
//// }
//// else if(TEMPSEL == 1)
//// {
//// GpioDataRegs.GPCSET.bit.GPIO68 = 1;
//// GpioDataRegs.GPCCLEAR.bit.GPIO69 = 1;
////
//// }
//// else if(TEMPSEL == 2)
//// {
//// GpioDataRegs.GPCCLEAR.bit.GPIO68 = 1;
//// GpioDataRegs.GPCSET.bit.GPIO69 = 1;
//// }
//// else if(TEMPSEL == 3)
//// {
//// GpioDataRegs.GPCSET.bit.GPIO68 = 1;
//// GpioDataRegs.GPCSET.bit.GPIO69 = 1;
//// }
// TempIGBT_Sel0 = TEMPSEL & 0x1;
// TempIGBT_Sel1 = TEMPSEL >> 1;
// TEMPSEL++;
// if(TEMPSEL >= 4)
// {
// TEMPSEL = 0;
// }
//}
interrupt void CpuTimer0_ISR(void)
{
//GpioDataRegs.GPCTOGGLE.bit.GPIO88 = 1;
CpuTimer0.InterruptCount++;
if(CpuTimer0.InterruptCount >= 100)
{
CpuTimer0.InterruptCount = 0;
//DisplayChartHEX(AdcResults, 12);
//DisplayChartHEX(AdcIgrid, 3);
//DisplayChartHEX(&AdcItrack[0], 1);
//DisplayChartHEX(AdcVgrid, 3);
//DisplayChartHEX(&AdcVdc, 1);
}
CpuTimer0Regs.TCR.bit.TIF = 1;
CpuTimer0Regs.TCR.bit.TRB = 1;
PieCtrlRegs.PIEACK.bit.ACK1 = 1;
}
/****************************************************************
* 2ms state change
*************************************************************/
interrupt void CpuTimer1_2ms_ISR(void)
{
Toggle_Led90();
if ((Sys_Current_State == State_Check) || (Sys_Current_State == State_PreCharge) || (Sys_Current_State == State_Running))
{
if (Peripheral_Switch_State.bit.Key_Stop == 1)
{
StateUpdate_ParaInit_Once = 0;
Sys_Current_State = State_Stop;
}
}
Check_HardwarePro();
StateSwitch();
if (Sys_Current_State == State_PreCharge) //vdc soft start
{
if (All_State_Flag.bit.Vdc_Slowup == 1)
{
Slowup_Vdc_Ref();
// EPwm6Regs.CMPB.bit.CMPB = Vdc_Ref.Ref_CMD * 1.125f;//D=0.45 1.125 D=0.4 1.0
// //D=0.5 1.25 1.5 D=0.6 1.5//500V -> duty 0.75 -> 938, 938 / 500 = 1.875
// EPwm6Regs.CMPA.bit.CMPA = Vdc_Ref.Ref_CMD * 1.125f;
//ref:500V,TBPRD1250,D=CMPA/1250,cmpa=x*500
EPwm6Regs.CMPB.bit.CMPB = Vdc_Ref.Ref_CMD * 1.102f;//D=0.45 1.102
EPwm6Regs.CMPA.bit.CMPA = Vdc_Ref.Ref_CMD * 1.102f;
//ref:510V,TBPRD1250,D=CMPA/1250,cmpa=x*510
}
}
if (Sys_Current_State == State_Running) //Itrack soft start
{
if (All_State_Flag.bit.Itrack_Slowup == 1)
{
Slowup_Itrack_Ref();
EPwm8Regs.TBPHS.bit.TBPHS = 1180 - Itrack_Ref.Ref_CMD * 23.6f;
// EPwm8Regs.TBPHS.bit.TBPHS = 1180 - Itrack_Ref.Ref_CMD * 39.3f;
}
}
// if ((Sys_Current_State == State_Running)||(Sys_Current_State == State_PreCharge))
// {
// GpioDataRegs.GPCSET.bit.GPIO86 = 1;
// }
// else
// {
// GpioDataRegs.GPCCLEAR.bit.GPIO86 = 1;
// }
// if (Sys_Current_State == State_Running)
// {
// if(GpioDataRegs.GPADAT.bit.GPIO22 == 0)
// {
// Vdc_Ref.Ref = 510.0f;
// Vdc_Ref.Ref_CMD = 510.0f;
// Vdc_Ctrl_PI.Upper_Limit = 0.8f;
// }
//// if(GpioDataRegs.GPADAT.bit.GPIO22 == 1)
//// {
//// Vdc_Ref.Ref = 250.0f;
//// Vdc_Ref.Ref_CMD = 250.0f;
//// Vdc_Ctrl_PI.Upper_Limit = 0.45f;
//// }
// }
// if (Sys_Current_State == State_Running)
// {
// if(Vdc_Ref.Ref_CMD == 510.0f)
// {
// if(GpioDataRegs.GPADAT.bit.GPIO22 == 1)
// {
// check_Vdctime++;
// if(check_Vdctime>=17500)
// {
// Vdc_Ref.Ref = 250.0f;
// Vdc_Ref.Ref_CMD = 250.0f;
// Vdc_Ctrl_PI.Upper_Limit = 0.45f;
// check_Vdctime=0;
// }
//
// }
//
// }
// }
// if ( (Sys_Current_State == State_Running) || (Sys_Current_State == State_PreCharge) )
// {
// if( (Vdc_Ref.Ref_CMD >=240) && (Vdc_Ref.Ref_CMD <=250) )
// {
// GpioDataRegs.GPCCLEAR.bit.GPIO86 = 1;
// }
// }
// else
// {
// GpioDataRegs.GPCSET.bit.GPIO86 = 1;
// }
//
// if (Sys_Current_State == State_Running)
// {
// if(GpioDataRegs.GPADAT.bit.GPIO22 == 1)
// {
//// if( Sample_CalcResult.Track_Ave <= 1.0f)
//// {
// Vdc_Ref.Ref = 510.0f;
// Vdc_Ref.Ref_CMD = 510.0f;
// Vdc_Ctrl_PI.Upper_Limit = 0.85f;
//// }
//// else
//// {
//// Fault_Flag.bit.Fault_Generate = 1;
//// }
// }
// if(GpioDataRegs.GPADAT.bit.GPIO22 == 0)
// {
// Vdc_Ref.Ref = 250.0f;
// Vdc_Ref.Ref_CMD = 250.0f;
// Vdc_Ctrl_PI.Upper_Limit = 0.55f;
// }
// }
if (Sys_Current_State == State_Running)
{
if ((Sample_CalcResult.TempIGBT1 >= 85.0f) ||
(Sample_CalcResult.TempIGBT2 >= 85.0f) ||
(Sample_CalcResult.TempIGBT3 >= 85.0f) ||
(Sample_CalcResult.TempIGBT4 >= 85.0f))
// (Sample_CalcResult.TempIGBT5 >= 85.0f) ||
// (Sample_CalcResult.TempIGBT6 >= 85.0f) ||
// (Sample_CalcResult.TempIGBT7 >= 85.0f) ||
// (Sample_CalcResult.TempIGBT8 >= 85.0f)
{
Fault_Flag.bit.temp_warming = 1;
}
if (Peripheral_Switch_State.bit.Key_Reset == 1)
{
Clear_AllFault();
}
}
}
/************************************************`****************
* 20ms RMS AVE CALCULATION
* SOFT START
*************************************************************/
interrupt void CpuTimer2_20ms_ISR(void)
{
Task_GridPeriod();
if (Sys_Current_State == State_Running) //vdc crtl
{
Run_Vdc_Ctrl();
EPwm6Regs.CMPB.bit.CMPB = Vdc_Ctrl_PI.PI_Out * 1250.0f;
EPwm6Regs.CMPA.bit.CMPA = Vdc_Ctrl_PI.PI_Out * 1250.0f;
}
}
/****************************************************************
* AD INTERRUPT
* get real value
* clear interrupt flag
* close loop control
*************************************************************/
interrupt void Adcd_ISR(void)
{
// AdcResults[0] = (float)AdcaResultRegs.ADCRESULT0;//A0 VgridA
// AdcResults[1] = (float)AdcbResultRegs.ADCRESULT0;//B0 VgridC
// AdcResults[2] = (float)AdccResultRegs.ADCRESULT0;//C2 IgridA
// AdcResults[3] = (float)AdcdResultRegs.ADCRESULT0;//D1 IHbridge
// AdcResults[4] = (float)AdcbResultRegs.ADCRESULT1;//B2 VgridB
// AdcResults[5] = (float)AdccResultRegs.ADCRESULT1;//C3 IgridB
// AdcResults[6] = (float)AdcdResultRegs.ADCRESULT1;//D2 Itrack
// AdcResults[7] = (float)AdcbResultRegs.ADCRESULT2;//B3 Vdc
// AdcResults[8] = (float)AdccResultRegs.ADCRESULT2;//C4 IgridC
// AdcResults[9] = (float)AdcdResultRegs.ADCRESULT2;//D3 Itrack
// AdcResults[10] = (float)AdcdResultRegs.ADCRESULT3;//D4 TempIGBT
// AdcResults[11] = (float)AdcaResultRegs.ADCRESULT15;//A15 Vref
// AdcResults[0] = (float)AdcaResultRegs.ADCRESULT0;//A0 VgridA
// AdcResults[1] = (float)AdcbResultRegs.ADCRESULT1;//B2 VgridB
// AdcResults[2] = (float)AdcbResultRegs.ADCRESULT0;//B0 VgridC
// AdcResults[3] = (float)AdccResultRegs.ADCRESULT0;//C2 IgridA
// AdcResults[4] = (float)AdccResultRegs.ADCRESULT1;//C3 IgridB
// AdcResults[5] = (float)AdccResultRegs.ADCRESULT2;//C4 IgridC
// AdcResults[6] = (float)AdcbResultRegs.ADCRESULT2;//B3 Vdc
// AdcResults[7] = (float)AdcdResultRegs.ADCRESULT1;//D2 Itrack
// AdcResults[8] = (float)AdcdResultRegs.ADCRESULT2;//D3 Itrack
// AdcResults[9] = (float)AdcdResultRegs.ADCRESULT0;//D1 IHbridge
// AdcResults[10] = (float)AdcdResultRegs.ADCRESULT3;//D4 TempIGBT
// AdcResults[11] = (float)AdcaResultRegs.ADCRESULT15;//A15 Vref
// if(TEMPSEL == 0) TEMPResults[0] = (float)AdcdResultRegs.ADCRESULT3;//D4 TempIGBT
// else if(TEMPSEL == 1) TEMPResults[1] = (float)AdcdResultRegs.ADCRESULT3;//D4 TempIGBT
// else if(TEMPSEL == 2) TEMPResults[2] = (float)AdcdResultRegs.ADCRESULT3;//D4 TempIGBT
// else if(TEMPSEL == 3) TEMPResults[3] = (float)AdcdResultRegs.ADCRESULT3;//D4 TempIGBT
// AdcIgrid[0] = (float)((AdccResultRegs.ADCRESULT0 - 1861.81f) * 1.61133E-03f);
// AdcIgrid[1] = (float)((AdccResultRegs.ADCRESULT1 - 1861.81f) * 1.61133E-03f);
// AdcIgrid[2] = (float)((AdccResultRegs.ADCRESULT2 - 1861.81f) * 1.61133E-03f);
// AdcItrack[0] = (float)((AdcdResultRegs.ADCRESULT1 - 8.05E-4f) * 1.0f);
//AdcVdc = (float)((ADResultReg_Vdc - 2.0f) * 0.152472f);//ok
// AdcVgrid[0] = (float)((ADResultReg_Vgrid_Phase_A - 1851.89f) * 1.0f);
// AdcVgrid[1] = (float)((ADResultReg_Vgrid_Phase_B - 1851.81f) * 1.0f);
// AdcVgrid[2] = (float)((ADResultReg_Vgrid_Phase_C - 1851.81f) * 1.0f);
Get_Sample_RealValue();
Calc_Sample_AccValue();
if ((Sys_Current_State != State_Stop) && (Sys_Current_State != State_Fault))
{
if (All_State_Flag.bit.ADOffset_CheckOver == 1)
{
SoftWare_FastProtect();
}
}
//Vdc_PI
// if ((Sys_Current_State == State_PreCharge) || (Sys_Current_State == State_Running)) //vdc crtl
// {
// Run_Vdc_Ctrl();
// EPwm6Regs.CMPB.bit.CMPB = Vdc_Ctrl_PI.PI_Out * 1250.0f;
// EPwm6Regs.CMPA.bit.CMPA = Vdc_Ctrl_PI.PI_Out * 1250.0f;
// }
//Vdc_PI
// if (Sys_Current_State == State_Running) //vdc crtl
// {
// Run_Vdc_Ctrl();
// EPwm6Regs.CMPB.bit.CMPB = Vdc_Ctrl_PI.PI_Out * 1250.0f;
// EPwm6Regs.CMPA.bit.CMPA = Vdc_Ctrl_PI.PI_Out * 1250.0f;
// }
AdcdRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
if(1 == AdcdRegs.ADCINTOVF.bit.ADCINT1)// Check if overflow has occurred
{
AdcdRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; //clear INT1 overflow flag
AdcdRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
}
PieCtrlRegs.PIEACK.bit.ACK1 = 1;
}
interrupt void AD_ISR(void)
{
// if ((Sys_Current_State == State_PreCharge) && (Sys_Current_State == State_Running))
// {
// Run_Irack_Ctrl();
// }
}
interrupt void SciaModbusRxFifo_ISR(void)
{
if(SciaRegs.SCIRXST.bit.RXERROR == 1)
{
SciaRegs.SCICTL1.bit.SWRESET = 0;
SciaRegs.SCIFFRX.bit.RXFIFORESET = 0;
SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;
SciaRegs.SCICTL1.bit.SWRESET = 1;
}
else
{
Uint16 i;
for(i = 0; i < 8; i++)
{
Rx_ADU_Buffer[i] = SciaRegs.SCIRXBUF.bit.SAR;
}
modbus485_flag = 1;
}
SciaRegs.SCIFFRX.bit.RXFFOVRCLR = 1; // Clear Overflow flag
SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.bit.ACK9 = 1;
}
void LightBeepCMD(void)
{
switch (Sys_Current_State)
{
case State_Idle:
{
Light_Yellow_Off();
Light_Green_On();
Light_Red_Off();
// Beep_Off();
break;
}
case State_Fault:
{
Light_Yellow_On();
Light_Green_Off();
Light_Red_Off();
// Beep_On();
break;
}
default:
{
Light_Yellow_Off();
Light_Green_Off();
Light_Red_On();
if (Sys_Current_State == State_Check)
{
// Beep_On();
}
else
{
// Beep_Off();
}
if (Sys_Current_State == State_Running)
{
if(Fault_Flag.bit.Relay_Fan_Fault == 1 || Fault_Flag.bit.temp_warming == 1)
{
Light_Yellow_On();
Light_Green_Off();
Light_Red_Off();
}
}
break;
}
}
}
