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CPU1的代码在RAMLS、RAMGS都可正常运行CPU2的代码设置在RAMLS可以正常运行，设置在RAMGS运行出错，调用堆栈显示会_system_post_cinit() 0x3FE00A
您好，请参考TMS320F28388D: Trouble Booting 2nd Core when placing .bss and .data inside of RAMGS instead of RAMLS - C2000 microcontrollers forum - C2000︎ microcontrollers - TI E2E support forums
GS RAM 的所有权分配由 CPU1 完成，必须先运行CPU1的工程，再loadCPU2的工程
