LLC谐振套件软件程序问题

xiaopu chen

请问下面这个构建3程序，使用的是模拟比较器来控制后级同步整流管的开通和关断，具体运行原理是什么，望TI的老师帮我讲解一下，不胜感激。我自己没能看懂啊。

#if (INCR_BUILD == 3) // Closed Loop PID with SR timing based on Current (and Primary switches)
// Configure SR current trips
EALLOW;
// Configure Analog Comparators
Comp1Regs.COMPCTL.bit.SYNCSEL = 1; // Sync with SYSCLK / use Qualification
Comp1Regs.COMPCTL.bit.QUALSEL = 3; // Require input be stable for 3 consecutive SYSCLKs
Comp1Regs.COMPCTL.bit.CMPINV = 1; // Output Low when true
Comp1Regs.COMPCTL.bit.COMPSOURCE = 0; // Use internal DAC
Comp1Regs.COMPCTL.bit.COMPDACEN = 1; // Enable DAC
Comp1Regs.DACVAL.bit.DACVAL = COMP1; // Trip Current = DACVAL/1023*82.5

Comp2Regs.COMPCTL.bit.SYNCSEL = 1; // Sync with SYSCLK / use Qualification
Comp2Regs.COMPCTL.bit.QUALSEL = 3; // Require input be stable for 3 consecutive SYSCLKs
Comp2Regs.COMPCTL.bit.CMPINV = 1; // Output Low when true
Comp2Regs.COMPCTL.bit.COMPSOURCE = 0; // Use internal DAC
Comp2Regs.COMPCTL.bit.COMPDACEN = 1; // Enable DAC
Comp2Regs.DACVAL.bit.DACVAL = COMP2; // Trip Current = DACVAL/1023*82.5

// Configure ePWM Digital Compare modules
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; // DCAH = Comparator 1 output
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_LOW; // DCAEVT1 on DCAH low (will become active as Comparator1 output goes low), DCAL = don't care
EPwm2Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT_FLT; // DCAEVT1 filtered
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; // Take async path
EPwm2Regs.DCFCTL.bit.BLANKE = DC_BLANK_ENABLE; // Enable Blanking window
EPwm2Regs.DCFCTL.bit.SRCSEL = DC_SRC_DCAEVT1; // Filter source = DCAEVT1
EPwm2Regs.DCFCTL.bit.PULSESEL = DC_PULSESEL_ZERO; // Filter start on TBCTR = ZERO
EPwm2Regs.DCFOFFSET = 0; // Filter offset
EPwm2Regs.DCFWINDOW = 0; // Blanking window duration

EPwm3Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP2OUT; // DCAH = Comparator 2 output
EPwm3Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_LOW; // DCAEVT1 on DCAH low (will become active as Comparator2 output goes low), DCAL = don't care
EPwm3Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT_FLT; // DCAEVT1 filtered
EPwm3Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; // Take async path
EPwm3Regs.DCFCTL.bit.BLANKE = DC_BLANK_ENABLE; // Enable Blanking window
EPwm3Regs.DCFCTL.bit.SRCSEL = DC_SRC_DCAEVT1; // Filter source = DCAEVT1
EPwm3Regs.DCFCTL.bit.PULSESEL = DC_PULSESEL_ZERO; // Filter start on TBCTR = ZERO
EPwm3Regs.DCFOFFSET = 0; // Filter offset
EPwm3Regs.DCFWINDOW = 0; // Blanking window duration

// Configure ePWM Trip-Zone module
EPwm2Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_HI; // EPWM2A will go HIGH

EPwm3Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_HI; // EPWM3A will go HIGH

EDIS;

#endif // (INCR_BUILD == 3)

9 年多前

0 Martin Yu 9 年多前

TI__Expert 8058 points

这一段只是利用ADC的比较模块来限制同步整流部分的电流值，设定的电流上限是DACVAL/1023*82.5，如果ADC口上检测到的电流大于这个参考值时，COMP模块输出低电平，PWM模块和COMP模块连接在一起，当PWM的ET模块检测到COMP过来的低电平则触发TZ来强制PWM输出口状态为高电平。

 Use the analog comparators to dynamically adjust the SR PWM turn-off timing based on SR current levels.

0 xiaopu chen 9 年多前回复 Martin Yu

Expert 2590 points

首先十分感谢您对我的困惑给予详细的解答，谢谢。我当时也是这么理解的，但是我的疑惑是：当ADC采样到的同步整流管电流值大于比较器模块的设定值时，comp模块输出低电平，然后pwm模块的ET模块检测到comp过来的低电平时触发TZ来强制PWM输出为高。PWM强制为高时，此时同步整流管的MOSFET是导通的。但是何时将同步整流MOSFET关断呢？是如何关断的呢？因为同步整流管导通之后肯定还是需要关断的啊，不关断的话不行的啊。期待您解答一下我的疑惑，再次感谢。