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F28069的SPI引脚无信号

Tingyong Wu
Prodigy 10 points
Other Parts Discussed in Thread: AFE031

按照TI推荐的电路，设计了F28069和AFE031芯片的SPI接口使用了F28069的SPI-B信号，其中SPISIMO信号选择了使用Pin77（80Pin的F28069，77脚为GPIO24）.

SPI-B的管脚定义如下：

GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pullup on GPIO24 (SPISIMOB)
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pullup on GPIO13 (SPISOMIB)
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pullup on GPIO14 (***)
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pullup on GPIO15 (SPISTEB)
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 3; // asynch input
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // asynch input
GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // asynch input
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // asynch input
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; // GPIO24 = SPISIMOB
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // GPIO13 = SPISOMIB
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // GPIO14 = ***
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // GPIO15 = SPISTEB

SPI-B的寄存器配置如下：

SpibRegs.***.bit.SPISWRESET = 0; // reset SPISTS to clear flags
SpibRegs.***.bit.CLKPOLARITY = 0; // data is output on rising edge and input on falling edge.
SpibRegs.***.bit.SPILBK = 0; // disables SPI loopback
SpibRegs.***.bit.*** = 0xF; // character length is 16, adapt to the input bit length of AFE031.
SpibRegs.SPIBRR = 0x007F; // SYSCLKOUT: 80MHz, LSPCLK: 20MHz, SPI Baud Rate: ??Mbps
SpibRegs.***.bit.MASTER_SLAVE = 1; // master mode
SpibRegs.***.bit.TALK = 1; // enables sent data ???
SpibRegs.***.bit.CLK_PHASE = 1; // half-cycle delay
SpibRegs.***.bit.SPIINTENA = 0; // disables interrupt
SpibRegs.***.bit.OVERRUNINTENA = 0; // disables receiver overrun flag
SpibRegs.SPIFFTX.all = 0x0000; // disable SPI FIFO enhancements
SpibRegs.SPIFFRX.all = 0x0000;
SpibRegs.SPIPRI.bit.FREE = 1; // Free run
SpibRegs.***.bit.SPISWRESET = 1; // ready to transmit or receive

编译通过顺利加载，可以看到系统时钟部分的配置完成（锁相环已经锁定），上述的配置已经写入寄存器，发送数据也写入到SPITXBUF和SPIDAT，但管脚上就是没有信号。请问这是什么问题？谢谢！

  • 0
    Guru 56631 points

    初始化SPI-B的   对比一下

    EALLOW;
    /* Enable internal pull-up for the selected pins */
    // Pull-ups can be enabled or disabled by the user.
    // This will enable the pullups for the specified pins.
    // Comment out other unwanted lines.

    GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (SPISIMOB)
    GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (SPISOMIB)
    GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (SPICLKB)
    GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (SPISTEB)

    // GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (SPISIMOB)
    // GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (SPISOMIB)
    // GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (SPICLKB)
    // GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (SPISTEB)

    /* Set qualification for selected pins to asynch only */
    // This will select asynch (no qualification) for the selected pins.
    // Comment out other unwanted lines.

    GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Asynch input GPIO12 (SPISIMOB)
    GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (SPISOMIB)
    GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (SPICLKB)
    GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SPISTEB)

    // GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 3; // Asynch input GPIO24 (SPISIMOB)
    // GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO25 (SPISOMIB)
    // GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO26 (SPICLKB)
    // GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO27 (SPISTEB)

    /* Configure SPI-B pins using GPIO regs*/
    // This specifies which of the possible GPIO pins will be SPI functional pins.
    // Comment out other unwanted lines.

    GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // Configure GPIO12 as SPISIMOB
    GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // Configure GPIO13 as SPISOMIB
    GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // Configure GPIO14 as SPICLKB
    GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // Configure GPIO15 as SPISTEB

    // GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; // Configure GPIO24 as SPISIMOB
    // GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; // Configure GPIO25 as SPISOMIB
    // GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; // Configure GPIO26 as SPICLKB
    // GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3; // Configure GPIO27 as SPISTEB

  • 0 回复 mangui zhang
    Guru 56631 points

    没使用fifo吧

    SpiaRegs.SPICCR.all =0x000F; // Reset on, rising edge, 16-bit char bits
    SpiaRegs.SPICTL.all =0x0006; // Enable master mode, normal phase,
    // enable talk, and SPI int disabled.
    SpiaRegs.SPIBRR =0x007F;
    SpiaRegs.SPICCR.all =0x009F; // Relinquish SPI from Reset
    SpiaRegs.SPIPRI.bit.FREE = 1; // Set so breakpoints don't disturb xmission