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// Select Internal Oscillator 1 as Clock Source (default), and turn off all unused clocks to // conserve power. IntOsc1Sel(); // 配置时钟源，你可以先用内部时钟先测试一下
// Initialize the PLL control: PLLCR and CLKINDIV // DSP28_PLLCR and DSP28_CLKINDIV are defined in F2806x_Examples.h InitPll(DSP28_PLLCR,DSP28_DIVSEL); //分频，这个配置后系统就输出xxMHz的SYSCLKOUT
/*----------------------------------------------------------------------------- Specify the PLL control register (PLLCR) and clock in divide (CLKINDIV) value.
if CLKINDIV = 0: SYSCLKOUT = (OSCCLK * PLLCR)/2 if CLKINDIV = 1: SYSCLKOUT = (OSCCLK * PLLCR) -----------------------------------------------------------------------------*/ #define DSP28_CLKINDIV 0 // Enable /2 for SYSCLKOUT //#define DSP28_CLKINDIV 1 // Disable /2 for SYSCKOUT
如果你是六倍的话 就是 25*6=150 然后还有一个 Enable /2 for SYSCLKOUT 就是75 了
这里把75的屏蔽去掉
//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) #define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 16.667L // for a 60MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
