TMS320F280039C: CMPSS(DACL is higher than DACH) + CLB PWM resolution as to the PMP41081 (current mode LLC) design

I have two questions about PMP41081 (current mode LLC) reference design.

Q1<CMPSS>：“The DACH setting must always be higher than the DACL setting.” Quoted from the “Reference DAC” section, “CMPSS part”, TRM.

But in the design: CMPSS1PH is used for current mode control(A11/B11/C0), while CMPSS1PL is used for Primary side OCP(B6).

     DACLVALA=(i.e. 58A/60A*4095=3958) for OCP.

     In a word, it seems that the DACH setting CAN NOT always be higher than the DACL setting.
So what is the bad consequence? How bad is it?

Q2<PWM resolution with CLB>: It seems that HRPWM is not possible to be used in this control method. In addtion, CLB clock is no more than 150MHz (28P65x). Considering the 200M CPU CLK, the PWM CLK/CLB timer is 100M for 28P65x.

So the final PWM resolution is 10ns @100MHz PWM Frequency.
Any suggestion to improve the PWM resolution?

Thanks in advance!