DSP28335接收GPS信号并解析的问题

//Q：只验证接收，并没有解析，但是却是收不到正确的数据帧。（GPS数据是以$GP开头的数据帧）如图所示：感觉//数据接收存在问题， Buf=(ScibRegs.SCIRXBUF.all) & 0x00FF;
//采用的是中断方式。
//拜托有懂的大神帮忙看看，本人小白一只，不胜感激。

/*
 * Example_2833xSci_FFDLB_int_2.c
 *
 *  Created on: 2016-4-22
 *      Author: King
 */

#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File

#define CPU_FREQ      150E6
#define LSPCLK_FREQ  CPU_FREQ/4
#define SCI_FREQ      100E3
#define SCI_PRD      (LSPCLK_FREQ/(SCI_FREQ*8))-1


interrupt void scibRxFifoIsr(void);


void scib_fifo_init(void);

void error(void);

int ScibRX_Ready(void);

char Buf[100];

unsigned int i;
unsigned int flag=0;


void main(void)
{

   InitSysCtrl();
   InitSciGpio();
   DINT;
   InitPieCtrl();
   IER = 0x0000;
   IFR = 0x0000;
   InitPieVectTable();
   EALLOW;    // This is needed to write to EALLOW protected registers

   PieVectTable.SCIRXINTB = &scibRxFifoIsr;


   EDIS;   // This is needed to disable write to EALLOW protected registers


   scib_fifo_init();  // Init SCI-B

   PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
   PieCtrlRegs.PIEIER9.bit.INTx1=1;     // PIE Group 9, int1
   PieCtrlRegs.PIEIER9.bit.INTx2=1;     // PIE Group 9, INT2
   PieCtrlRegs.PIEIER9.bit.INTx3=1;     // PIE Group 9, INT3
   PieCtrlRegs.PIEIER9.bit.INTx4=1;     // PIE Group 9, INT4

   IER = 0x100;    // Enable CPU INT
   EINT;


    for(;;);

}

void error(void)
{
    asm("     ESTOP0"); // Test failed!! Stop!
    for (;;);
}
interrupt void scibRxFifoIsr(void)
{

    for(i=0;i<8;i++)
    {
            Buf[flag*8+i]=(ScibRegs.SCIRXBUF.all) & 0x00FF;
    }
        if(flag>=10)
           flag=0;
        flag++;

        ScibRegs.SCIFFRX.bit.RXFFOVRCLR=1;  // Clear Overflow flag
        ScibRegs.SCIFFRX.bit.RXFFINTCLR=1;     // Clear Interrupt flag
        PieCtrlRegs.PIEACK.all|=0x100;      // Issue PIE ack
}
 void scib_fifo_init()
{
   ScibRegs.SCICCR.all =0x0007;    // 1 stop bit,  No loopback
                                   // No parity,8 char bits,
                                   // async mode, idle-line protocol
   ScibRegs.SCICTL1.all =0x0003;   // enable TX, RX, internal SCICLK,
                                   // Disable RX ERR, SLEEP, TXWAKE
   ScibRegs.SCICTL2.bit.TXINTENA =1;
   ScibRegs.SCICTL2.bit.RXBKINTENA =1;
   ScibRegs.SCIHBAUD    =0x0001;
   ScibRegs.SCILBAUD    =0x00E7;
   ScibRegs.SCICCR.bit.LOOPBKENA =0; // Enable loop back
   ScibRegs.SCIFFTX.all=0xC023;
   ScibRegs.SCIFFRX.all=0x0028;
   ScibRegs.SCIFFCT.all=0x00;

   ScibRegs.SCICTL1.all =0x0023;     // Relinquish SCI from Reset
   ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1;
   ScibRegs.SCIFFRX.bit.RXFIFORESET=1;

}
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// No more.
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