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GPACSEL1 is shown in Figure 7-15 and described in Table 7-25. Return to Summary Table. GPIO A Core Select Register (GPIO0 to 7) Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin xx00: CPU1 selected xx01: CPU1.CLA1 selected xx10: CPU2 selected xx11: CPU2.CLA1 selected
15-12 GPIO3 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
