关于TMDSHV1PHINVKIT在线调试与CCS联机问题

1. 如果要实时看变量而且有些时候还要设断点，建议升级到最新的CCS6版本，这个版本不用点击real time的模式，可以直接点击expression窗口的连续刷新按钮就可以实时看变量更新了。

2. 如果在大功率的调试中，想要设断点，又怕损坏电路，建议使用以下功能：

PWM有一个TZ6信号，这个信号是连仿真器时，暂停或断点的时候会产生的信号，可以配置TZ模块用这个信号来关掉PWM。

// -Cycle by cycle trip on CPU halt
// -One shot fault trip zone
// These trips need to be repeated for EPWM1 ,2 & 3
EALLOW;
EPwm1Regs.TZSEL.bit.CBC6=0x1; // TZ6 in CBC
EPwm2Regs.TZSEL.bit.CBC6=0x1;
EPwm3Regs.TZSEL.bit.CBC6=0x1;

//No TZ1 select
EPwm1Regs.TZSEL.bit.OSHT1 = 1; //enable TZ1 for OSHT
EPwm2Regs.TZSEL.bit.OSHT1 = 1; //enable TZ1 for OSHT
EPwm3Regs.TZSEL.bit.OSHT1 = 1; //enable TZ1 for OSHT

// What do we want the OST/CBC events to do
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low

EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low

EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low

// Clear any spurious OV trip
EPwm1Regs.TZCLR.bit.OST = 1;
EPwm2Regs.TZCLR.bit.OST = 1;
EPwm3Regs.TZCLR.bit.OST = 1;

EDIS;

这样当仿真器暂停的时候，PWM会在20ns内关掉，就不用担心损坏电路了。

Eric