F280x 的SCI RX中断导致 Illegal TRAP问题

huafeng wang

最近调试项目一个串口通讯功能，在project正常(PieCtrlRegs.PIEIER9.bit.INTx3 = 0; 时一切正常) 情况下，使能SCIB接收中断(PieCtrlRegs.PIEIER9.bit.INTx3 = 1;) 会导致非法中断。接收中断中基本什么都没有干，挂仿真器查看发现进了第一次中断接收到第一个字节（收到的这个字节是对的）后就再也进不了第二次接收中断，停在ILLEGAL_ISR中。

main()
{
......

InitPeripherals();

EALLOW;
PieVectTable.EPWM1_INT = &PWM_LOAD_ISR;
PieVectTable.SCIRXINTB = &SWI_SCIBRX_ISR;
EDIS;

PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER9.bit.INTx3 = 1;

IER |= M_INT3;
IER |= M_INT13;
IER |= M_INT9;

......
}

InitPeripherals ()中对SCI初始化如下(这段初始化是从另一个能正常串口通讯的28335项目移植的)：

ScibRegs.SCICCR.all = 0x0007;
ScibRegs.SCICTL1.all = 0x0003;
ScibRegs.SCICTL2.bit.TXINTENA = 1;
ScibRegs.SCICTL2.bit.RXBKINTENA = 1;

//9600 baud @LSPCLK = 25MHz.
ScibRegs.SCIHBAUD = 0x0001;
ScibRegs.SCILBAUD = 0x0044;

ScibRegs.SCIRXST.all = 0x00;
ScibRegs.SCIRXEMU = 0x00;
ScibRegs.SCIRXBUF.all = 0x00;
ScibRegs.SCITXBUF = 0x00;

ScibRegs.SCIFFTX.all = 0xE040;
ScibRegs.SCIFFRX.all = 0x6061;
ScibRegs.SCIFFCT.all = 0x00;
ScibRegs.SCIFFTX.bit.TXFIFOXRESET = 1;
ScibRegs.SCIFFRX.bit.RXFIFORESET = 1;
//ScibRegs.SCIPRI.all = 0x10;
ScibRegs.SCIPRI.bit.FREE = 1;
ScibRegs.SCICTL1.all = 0x0023;

接收中断如下：

void SWI_SCIBRX_ISR(void)
{
PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
PieCtrlRegs.PIEIER9.bit.INTx3 = 0;

SCI_RX_INT_PROCESS(SCIB_PORT);

ScibRegs.SCIFFRX.bit.RXFFOVRCLR = 1;
ScibRegs.SCIFFRX.bit.RXFFINTCLR = 1;
PieCtrlRegs.PIEIER9.bit.INTx3 = 1;
}

void SCI_RX_INT_PROCESS(Uint8 u8sciId)
{
Uint16 wRxData;

wRxData = ScibRegs.SCIRXBUF.all;
}

进一次SWI_SCIBRX_ISR() 后，继续运行便会停在如下非法中断里

interrupt void ILLEGAL_ISR(void)
{
EINT;

asm (" ESTOP0");

for(;;);
}

有哪位高手能知道原因吗？希望TI能尽快回复！

9 年多前