在cpu2配置ipc0-3中断后，在cpu1设置IpcRegs.IPCSET.bit.IPC0 = 1;后，为什么cpu2上相应的PIE中断标志并未被置位？IPC中的4个中断是如何产生的？
cpu2上中断配置如下：
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt Service Routines (ISR).
InitPieVectTable();
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.IPC0_INT = &IPC0_ISR;
PieVectTable.IPC1_INT = &IPC1_ISR;
PieVectTable.IPC2_INT = &IPC2_ISR;
PieVectTable.IPC3_INT = &IPC3_ISR;
EDIS; // This is needed to disable write to EALLOW protected registers
IER |= M_INT1;
PieCtrlRegs.PIEIER1.bit.INTx13 = 1;
PieCtrlRegs.PIEIER1.bit.INTx14 = 1;
PieCtrlRegs.PIEIER1.bit.INTx15 = 1;
PieCtrlRegs.PIEIER1.bit.INTx16 = 1;
InitIpc();
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
