28035关于IEC60730的codestart中POST一直失败，为什么啊 28035_IEC60730_FLASH.cmd文件已经添加，IEC60730.lib和头文件已经添加
DSP2803x_CodeStartBranch_IEC60730.asm中POST（Power On Self-Test）
;//===========================================================================
;// FILE: DSP2803x_CodeStartBranch.asm
;//
;// TITLE: Branch for redirecting code execution after boot.
;//===========================================================================
*********************************************************************** .include "psa.inc" WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 vars_util .usect "IEC60730_PASS_FAIL",3,1 ;vars on same data page expectedCRC_8k_L0RamTest_LOW .long 0x89E210D4 ;28035_28034_28033_28032 RAM CRC .sect "codestart" code_start: ;end codestart section *********************************************************************** .text RAM_Common_Testing: MOV @SP, #__stack ;TRUE for both 0xBF and 0xBE, PARTNO_28035PN and PARTNO_28035PAG ;TRUE for both 0xB6 and 0xB7, PARTNO_28033PAG and PARTNO_28033PN ;TRUE for both 0xAE and 0xAF, PARTNO_28031PAG and PARTNO_28031PN ;TRUE for both 0xAA and 0xAB, PARTNO_28030PAG and PARTNO_28030PN Test_28032_28033: Test_28031: Test_28030: NonRAM_Common_TESTS: PASS_TESTS: ;C Run-time CRC Calculation, allow choice of address range to give user ; push Save on Entry registers as specified by C conventions MOVL XAR3, ACC ; save start address passed parameter PSA_INIT_DRDB ; claim PSA and initialize to 0 ; ------------------------------------------------------- PSA_ON_DRDB ; monitor DRDB POP ST0 POP XAR1 ; restore resources ; store CRC result in ACC NASP ; un-align stack just in case .end .end
***********************************************************************
* Function: codestart section
*
* Description: Branch to code starting point
***********************************************************************
.cdecls C,LIST,"IEC60730_Tests.h"
.def _FLASH_test
.ref _c_int00, __stack
.global code_start
_PASS .set vars_util+0
_FAIL .set vars_util+1
_PART .set vars_util+2
.sect "EXPECTED_CRCs"
expectedCRC_M0M1RamTest .long 0xD0329384 ;Common RAM CRC
expectedCRC_PIERamTest .long 0x877078AB ;Common RAM CRC
expectedCRC_RomTest .long 0xBC9BF741 ;Common ROM CRC
expectedCRC_OTPCalTest1 .long 0xCE722B22 ;Common OTPCal CRC
expectedCRC_OTPCalTest2 .long 0x241263EA ;Common OTPCal CRC
expectedCRC_OTPCalTest3 .long 0x788A932C ;Common OTPCal CRC
expectedCRC_RegsTest .long 0x72D05672 ;Common CPU_REG CRC
expectedCRC_8k_L0RamTest_HIGH .long 0x2ED5F855 ;28035_28034_28033_28032 RAM CRC
expectedCRC_6k_L0RamTest_LOW .long 0xBC4A8AC0 ;28035_28034_28033_28032 RAM CRC
expectedCRC_6k_L0RamTest_HIGH .long 0x2ED5F855 ;28035_28034_28033_28032 RAM CRC
expectedCRC_4k_L0RamTest_LOW .long 0xB795DDDC ;28035_28034_28033_28032 RAM CRC
expectedCRC_4k_L0RamTest_HIGH .long 0x2ED5F855 ;28035_28034_28033_28032 RAM CRC
expectedCRC_64k_FlashTest .long 0xDF09FFDE ;28035_28034 FLASH CRC
expectedCRC_32k_FlashTest .long 0xB2AD181F ;28033_28032_28031 FLASH CRC
expectedCRC_16k_FlashTest .long 0xEB1C544B ;28030 FLASH CRC
***********************************************************************
* Function: codestart section
*
* Description: Branch to code starting point
***********************************************************************
.if WD_DISABLE == 1
LB wd_disable ;Branch to watchdog disable code
.else
LB _c_int00 ;Branch to start of boot.asm in RTS library
.endif
* Function: wd_disable
*
* Description: Disables the watchdog timer
***********************************************************************
.if WD_DISABLE == 1
wd_disable:
SETC OBJMODE ;Set OBJMODE for 28x object code
EALLOW ;Enable EALLOW protected register access
MOVZ DP, #7029h>>6 ;Set data page for WDCR register
MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD
EDIS ;Disable EALLOW protected register access
MOVZ DP, #_PASS ;Set data page
MOV @_PASS, #1
MOV @_FAIL, #0
;32-bit CRC returned in ACC, On passed test PASS=0 and FAIL!=0
TEST_RAM M0M1_START_ADDR, M0M1_END_ADDR, expectedCRC_M0M1RamTest
TEST_RAM PIE_START_ADDR, PIE_END_ADDR, expectedCRC_PIERamTest
Part_Identification:
; check the PART ID register location
MOVL XAR7, #0x3D7FFF
MOVL ACC, *XAR7
MOVZ DP, #_PART ;Set data page
MOV @_PART, AH
;TRUE for both 0xBB and 0xBA, PARTNO_28034PN and PARTNO_28034PAG
CMP @_PART, #PARTNO_28034PAG
B Test_28035_28034,GEQ
;TRUE for both 0xB2 and 0xB3, PARTNO_28032PAG and PARTNO_28032PN
CMP @_PART, #PARTNO_28032PAG
B Test_28032_28033,GEQ
CMP @_PART, #PARTNO_28031PAG
B Test_28031,GEQ
CMP @_PART, #PARTNO_28030PAG
B Test_28030,GEQ
;32-bit CRC returned in ACC, On passed test PASS=0 and FAIL!=0
Test_28035_28034:
TEST_RAM L0RAM_8k_START_ADDR_LOW, L0RAM_8k_END_ADDR_LOW, expectedCRC_8k_L0RamTest_LOW ;8k_L0RamTest address map 1
TEST_RAM L0RAM_8k_START_ADDR_HIGH, L0RAM_8k_END_ADDR_HIGH, expectedCRC_8k_L0RamTest_HIGH ;8k_L0RamTest address map 2
CRC_CALC FLASH_START_ADDR_64k, FLASH_END_ADDR_64k, expectedCRC_64k_FlashTest ;32k_FlashTest
LB NonRAM_Common_TESTS
TEST_RAM L0RAM_8k_START_ADDR_LOW, L0RAM_8k_END_ADDR_LOW, expectedCRC_8k_L0RamTest_LOW ;8k_L0RamTest address map 1
TEST_RAM L0RAM_8k_START_ADDR_HIGH, L0RAM_8k_END_ADDR_HIGH, expectedCRC_8k_L0RamTest_HIGH ;8k_L0RamTest address map 2
CRC_CALC FLASH_START_ADDR_32k_3x, FLASH_END_ADDR_32k_3x, expectedCRC_32k_FlashTest ;32k_FlashTest
LB NonRAM_Common_TESTS
TEST_RAM L0RAM_6k_START_ADDR_LOW, L0RAM_6k_END_ADDR_LOW, expectedCRC_6k_L0RamTest_LOW ;6k_L0RamTest address map 1
TEST_RAM L0RAM_6k_START_ADDR_HIGH, L0RAM_6k_END_ADDR_HIGH, expectedCRC_6k_L0RamTest_HIGH ;6k_L0RamTest address map 2
CRC_CALC FLASH_START_ADDR_32k_3x, FLASH_END_ADDR_32k_3x, expectedCRC_32k_FlashTest ;32k_FlashTest
LB NonRAM_Common_TESTS
TEST_RAM L0RAM_4k_START_ADDR_LOW, L0RAM_4k_END_ADDR_LOW, expectedCRC_4k_L0RamTest_LOW ;4k_L0RamTest address map 1
TEST_RAM L0RAM_4k_START_ADDR_HIGH, L0RAM_4k_END_ADDR_HIGH_3x,expectedCRC_4k_L0RamTest_HIGH ;4k_L0RamTest address map 2
CRC_CALC FLASH_START_ADDR_16k, FLASH_END_ADDR_16k, expectedCRC_16k_FlashTest ;16k_FlashTest
LB NonRAM_Common_TESTS
CRC_CALC ROM_START_ADDR_2803x, ROM_END_ADDR_2803x, expectedCRC_RomTest
CRC_CALC OTP_CAL_START_ADDR1, OTP_CAL_END_ADDR1, expectedCRC_OTPCalTest1
CRC_CALC OTP_CAL_START_ADDR2, OTP_CAL_END_ADDR2, expectedCRC_OTPCalTest2
CRC_CALC OTP_CAL_START_ADDR3, OTP_CAL_END_ADDR3, expectedCRC_OTPCalTest3
TEST_CPU_REGS expectedCRC_RegsTest
LB _c_int00 ;Branch to start of boot.asm in RTS library
.endif
;control over lenght test time and resulting time that interrupts are disabled.
_FLASH_test:
PUSH DP:ST1 ; preserve original SPA bit in ST1
ASP ; Align stack just in case.
PUSH XAR1
PUSH XAR2
PUSH XAR3
MOVL XAR2, *-SP[12] ; save length passed parameter
loop:
; preserve resources used in memory test
PUSH XAR0
PUSH XAR1
; preserve contents of status registers (mainly INTM and SPA)
PUSH ST1
PUSH ST0
; set status registers to a known state
MOV *SP++,#0x024B ; ST1: ARP=0, XF=0, CNF=0, OBJMODE=1, AMODE=0,
; EALLOW=1, VMAP=1, PAGE0=0, DBGM=1, INTM=1
MOV *SP++,#0x0080 ; ST0: OVC=0, PM = 1, V=0, N=0, Z=0, C=0, TC=0, OVM=0, SXM=0
POP ST0 ; configure ST0
POP ST1 ; configure ST1 (interrupts disabled, debug disabled, EALLOW enabled)
; ------------- start uninterruptible code --------------
; -------------------------------------------------------
; Read memory range, values on bus will be in CRC by PSA
RPT AR2
|| ADDL ACC, *XAR3++
PSA_OFF_RELEASE
POP ST1 ; INTM is restored
; -------------------------------------------------------
; -------------- end uninterruptible code ---------------
; ------------- (interrupts serviced here) --------------
; -------------------------------------------------------
POP XAR0
EALLOW
MOVL ACC, *+XAR4[2]
EDIS
; pop Save on Entry registers as specified by C conventions
POP XAR3
POP XAR2
POP XAR1
POP DP:ST1 ; restore original SPA bit in ST1
LRETR
;//===========================================================================
;// End of file.
;//===========================================================================