void Uart1_Init(Uint16 baudrate)
{
EALLOW;
PieVectTable.SCIC_RX_INT = &UART1_RxFifoIsr;
PieVectTable.SCIC_TX_INT = &UART1_TxFifoIsr;
GpioCtrlRegs.GPCMUX2.bit.GPIO89 = 0;
GpioCtrlRegs.GPCMUX2.bit.GPIO90 = 0;
GpioCtrlRegs.GPCGMUX2.bit.GPIO89 = 1;
GpioCtrlRegs.GPCGMUX2.bit.GPIO90 = 1;
GpioCtrlRegs.GPCMUX2.bit.GPIO89 = 1; // SCITXDC
GpioCtrlRegs.GPCMUX2.bit.GPIO90 = 1; // SCIRXDC
GpioCtrlRegs.GPCPUD.bit.GPIO89 = 0; // Enable pullup on GPIO89
GpioCtrlRegs.GPCPUD.bit.GPIO90 = 0; // Enable pullup on GPIO90
GpioCtrlRegs.GPCQSEL2.bit.GPIO90 = 3; // asynch input
// Note: Clocks were turned on to the SCIA peripheral in the InitSysCtrl() function
ScicRegs.SCICCR.all = UART_STOP_BIT_1 | 0x0007; // 1 stop bit, No loopback, Even parity,8 char bits, async mode, idle-line protocol
ScicRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK, Disable RX ERR, SLEEP, TXWAKE
ScicRegs.SCICTL2.bit.TXINTENA = 1;
ScicRegs.SCICTL2.bit.RXBKINTENA = 1;
ScicRegs.SCIHBAUD.all = 0; // 115200 baud @LSPCLK = 50MHz (200 MHz SYSCLK).
ScicRegs.SCILBAUD.all = baudrate;
ScicRegs.SCIFFTX.all = 0xC000; // SCI reset, FIFO enable, reset the FIFO pointer to zero and hold in reset, transmit interrrupt disable, FIFO interrupt level 0
ScicRegs.SCIFFRX.all = 0x0021; // Transmit interrrupt enable, FIFO interrupt level 1
ScicRegs.SCIFFCT.all = 0x00; // Receive FIFO interrupt enable
ScicRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
ScicRegs.SCIFFTX.bit.TXFIFORESET = 1; // Re-enable transmit FIFO operation
ScicRegs.SCIFFRX.bit.RXFIFORESET = 1; // Re-enable receive FIFO operation
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER8.bit.INTx5 = 1; // PIE Group 8, INT5, RX
PieCtrlRegs.PIEIER8.bit.INTx6 = 1; // PIE Group 8, INT6, TX
IER |= M_INT8; // Enable CPU INT
EDIS;
}
void UART1_Send_test(Uint8 *buf, Uint8 count)
{
Uint8 i = 0;
for(i=0; i<count; i++)
ScicRegs.SCITXBUF.all = buf[i];
PieCtrlRegs.PIEIER8.bit.INTx6 = 0; // Disable PIE Group 8, INT6, TX
}