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请问一下F28335ADC模块的采样时间窗



在ADC模块reference guide中

ADC时钟由ADCCLKPS和CPS寄存器确定,但是后面有一个ACQ_PS寄存器是控制扩展采样保持器的脉冲?

 

请问这究竟是什么意思?采样时间窗究竟起什么作用?

In addition, the ADC can be
tailored to accommodate variations in source impedances by widening the sampling/acquisition period.
This is controlled by the ACQ_PS[3:0] bits in the ADCTRL1 register. These bits do not affect the
conversion portion of the S/H and conversion process, but do extend the length of time in which the
sampling portion takes by extending the start of the conversion pulse