TIDM-1001中交错并联到底是怎么实现的，程序中的EPWM相位寄存器为什么配置为2

最近在研究TIDM-1001    两相LLC交错并联均流，  打开例程后发现找不到相应的实现两相交错的程序，在EPWM寄存器配置中 也看不到相应的相位关系  相位寄存器(*ePWM[n+1]).TBPHS.bit.TBPHS = 2    我查了2837X的寄存器表 发现这一位只有置0和1，没有2    所以下请各位大神解答下疑问

1，如何实现交错并联的？

2，相位寄存器置2 是什么作用？

3，GLDCTL这个寄存器的实际作用是什么？

4，2837X的EPWM比较寄存器中多出了CMPC和CMPD，这两个又有什么用，是能输出四路信号吗？

下面贴出两相的PWM配置

第一相

(*ePWM[n]).TBCTL.bit.PRDLD = TB_SHADOW; // set load on CTR=0
(*ePWM[n]).TBPRD = period/2; // PWM frequency = 1 / period
(*ePWM[n]).TBPHS.bit.TBPHS = 0;
(*ePWM[n]).TBCTR = 0;
(*ePWM[n]).TBCTL.bit.FREE_SOFT = 3; // free run

(*ePWM[n]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
(*ePWM[n]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[n]).TBCTL.bit.CLKDIV = TB_DIV1;

// config as a Master
(*ePWM[n]).TBCTL.bit.PHSEN = TB_DISABLE;
(*ePWM[n]).TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // sync "down-stream"

// Counter Compare Submodule Registers
(*ePWM[n]).CMPA.bit.CMPA = 1; // Start with 50% duty (Avoid using CMP = 0)
(*ePWM[n]).CMPB.bit.CMPB = period/2 - 1; // Start with 50% duty (Avoid using CMP = PRD)
(*ePWM[n]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
(*ePWM[n]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
(*ePWM[n]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;
(*ePWM[n]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// if (mode == 0) // config as a Slave (Load on sync) - Not needed for 2-ph interleaved because of 180 deg phase shift obtained by AQ settings
// {
// (*ePWM[n]).CMPCTL.bit.LOADASYNC = 1; //Load on Sync and ZERO (configured above)
// (*ePWM[n]).CMPCTL.bit.LOADBSYNC = 1; //Load on Sync and ZERO (configured above)
// (*ePWM[n]).TBCTL2.bit.PRDLDSYNC = 1; //Load on Sync and ZERO (configured above)
// }

// Action Qualifier SubModule Registers
(*ePWM[n]).AQCTLA.bit.ZRO = AQ_CLEAR;
(*ePWM[n]).AQCTLA.bit.CAU = AQ_SET;
(*ePWM[n]).AQCTLA.bit.PRD = AQ_CLEAR;
// xB AQ output is inverted by DB for RED on xB output
(*ePWM[n]).AQCTLB.bit.PRD = AQ_SET;
(*ePWM[n]).AQCTLB.bit.CBD = AQ_CLEAR;
(*ePWM[n]).AQCTLB.bit.ZRO = AQ_SET;

(*ePWM[n]).AQSFRC.bit.RLDCSF = 0; //Load AQCSFRC on CTR = 0

// Active high complementary PWMs - Set up the deadband
(*ePWM[n]).DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
(*ePWM[n]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
(*ePWM[n]).DBCTL.bit.POLSEL = DB_ACTV_HIC;
(*ePWM[n]).DBCTL.bit.SHDWDBREDMODE = 1; // Enable shadow load for RED
(*ePWM[n]).DBCTL.bit.LOADREDMODE = 0; // Load on CTR = 0
(*ePWM[n]).DBCTL.bit.SHDWDBFEDMODE = 1; // Enable shadow load for RED
(*ePWM[n]).DBCTL.bit.LOADFEDMODE = 0; // Load on CTR = 0
(*ePWM[n]).DBRED = 15;
(*ePWM[n]).DBFED = 15;

(*ePWM[n]).GLDCFG.bit.TBPRD_TBPRDHR = 1;
(*ePWM[n]).GLDCFG.bit.CMPA_CMPAHR = 1;
(*ePWM[n]).GLDCFG.bit.CMPB_CMPBHR = 1;
(*ePWM[n]).GLDCFG.bit.CMPC = 1;
(*ePWM[n]).GLDCFG.bit.CMPD = 1;
(*ePWM[n]).GLDCFG.bit.DBRED_DBREDHR = 1;
(*ePWM[n]).GLDCFG.bit.DBFED_DBFEDHR = 1;
(*ePWM[n]).GLDCTL.bit.GLDMODE = 0; // Load on CTR = 0
// (*ePWM[n]).GLDCTL.bit.GLDMODE = 4; // Load on CTR = 0 and SYNC - Not needed for 2-ph interleaved
(*ePWM[n]).GLDCTL.bit.OSHTMODE = 1; // Enable one shot mode

(*ePWM[n]).GLDCTL.bit.GLD = 1; // Enable global load

第二相

(*ePWM[m]).TBCTL.bit.PRDLD = TB_SHADOW; // set load on CTR=0
(*ePWM[m]).TBPRD = period/2 - 1; // 'minus 1' to make sure that 1st cycle ends in CTR = 0 for PRD, CMP loads. Otherwise
// phase sync mechanism may not let the counter hit 0, instead loading it with 2.
// Only needed in the very first cycle after reset (or restart).
(*ePWM[m]).TBCTR = 0;
(*ePWM[m]).TBCTL.bit.FREE_SOFT = 3; // free run

(*ePWM[m]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
(*ePWM[m]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[m]).TBCTL.bit.CLKDIV = TB_DIV1;

// config as a Slave
(*ePWM[m]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[m]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
(*ePWM[m]).TBPHS.bit.TBPHS = 2;
(*ePWM[m]).TBCTL.bit.PHSDIR = 1; // Counter should count up after sync

// Counter Compare Submodule Registers
(*ePWM[m]).CMPA.bit.CMPA = 1; // Start with 50% duty (Avoid using CMP = 0)
(*ePWM[m]).CMPB.bit.CMPB = period/2 - 2; // Start with 50% duty (Avoid using CMP = PRD. Here TBPRD = period/2 - 1)
(*ePWM[m]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
(*ePWM[m]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
(*ePWM[m]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;
(*ePWM[m]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// if (mode == 0) // config as a Slave (Load on sync) - Not needed for 2-ph interleaved because of 180 deg phase shift obtained by AQ settings
// {
// (*ePWM[m]).CMPCTL.bit.LOADASYNC = 1; //Load on Sync and ZERO (configured above)
// (*ePWM[m]).CMPCTL.bit.LOADBSYNC = 1; //Load on Sync and ZERO (configured above)
// (*ePWM[m]).TBCTL2.bit.PRDLDSYNC = 1; //Load on Sync and ZERO (configured above)
// }

// Action Qualifier SubModule Registers
(*ePWM[m]).AQCTLA.bit.ZRO = AQ_CLEAR;
(*ePWM[m]).AQCTLA.bit.CBD = AQ_SET;
(*ePWM[m]).AQCTLA.bit.PRD = AQ_CLEAR;
// xB AQ output is inverted by DB for RED on xB output
(*ePWM[m]).AQCTLB.bit.ZRO = AQ_SET;
(*ePWM[m]).AQCTLB.bit.CAU = AQ_CLEAR;
(*ePWM[m]).AQCTLB.bit.PRD = AQ_SET;

(*ePWM[m]).AQSFRC.bit.RLDCSF = 0; //Load AQCSFRC on CTR = 0

// Active high complementary PWMs - Set up the deadband
(*ePWM[m]).DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
(*ePWM[m]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
(*ePWM[m]).DBCTL.bit.POLSEL = DB_ACTV_HIC;
(*ePWM[m]).DBCTL.bit.SHDWDBREDMODE = 1; // Enable shadow load for RED
(*ePWM[m]).DBCTL.bit.LOADREDMODE = 0; // Load on CTR = 0
(*ePWM[m]).DBCTL.bit.SHDWDBFEDMODE = 1; // Enable shadow load for RED
(*ePWM[m]).DBCTL.bit.LOADFEDMODE = 0; // Load on CTR = 0
(*ePWM[m]).DBRED = 15;
(*ePWM[m]).DBFED = 15;

(*ePWM[m]).GLDCFG.bit.TBPRD_TBPRDHR = 1;
(*ePWM[m]).GLDCFG.bit.CMPA_CMPAHR = 1;
(*ePWM[m]).GLDCFG.bit.CMPB_CMPBHR = 1;
(*ePWM[m]).GLDCFG.bit.CMPC = 1;
(*ePWM[m]).GLDCFG.bit.CMPD = 1;
(*ePWM[m]).GLDCFG.bit.DBRED_DBREDHR = 1;
(*ePWM[m]).GLDCFG.bit.DBFED_DBFEDHR = 1;
(*ePWM[m]).GLDCTL.bit.GLDMODE = 0; // Load on CTR = 0
// (*ePWM[m]).GLDCTL.bit.GLDMODE = 4; // Load on CTR = 0 and SYNC - Not needed for 2-ph interleaved
(*ePWM[m]).GLDCTL.bit.OSHTMODE = 1; // Enable one shot mode

(*ePWM[m]).GLDCTL.bit.GLD = 1; // Enable global load

望解答，不胜感激！