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ccs平台 mcu 编程过程中出现RAM不够的问题

changfu tan
Prodigy 70 points


问题描述，报错：

program will not fit into available memory.  placement with alignment fails for section ".cinit" size 0x132 Available memory ranges:

<Linking>
error #10056: symbol "_main" redefined: first defined in "./main.obj"; redefined in "./17k_slave_V0.02/app/main.obj"
warning #10247-D: creating output section "DataBuff" without a SECTIONS specification
warning #10247-D: creating output section "ramfuncs" without a SECTIONS specification
"../28332_RAM_lnk.cmd", line 134: error #10099-D: program will not fit into available memory. placement with alignment/blocking fails for section ".text" size 0x1f83 page 0. Available memory ranges:
RAML1 size: 0x1000 unused: 0x1000 max hole: 0x1000

undefined first referenced
symbol in file
--------- ----------------
_AdcResult ./17k_slave_V0.02/app/userisr.obj
_CpuTimer1Regs ./17k_slave_V0.02/app/userisr.obj
_ECap1Regs ./17k_slave_V0.02/app/userisr.obj
_EPwm3Regs ./17k_slave_V0.02/app/grid.obj
_GpioCtrlRegs ./17k_slave_V0.02/cpu/SCI_Boot.obj
_GpioDataRegs ./17k_slave_V0.02/app/spitask.obj
_I2caRegs ./17k_slave_V0.02/app/eeprom.obj
_OSEventGet ./17k_slave_V0.02/app/eeprom.obj
_OSEventSend ./17k_slave_V0.02/app/eeprom.obj
_OSIntExit ./17k_slave_V0.02/app/OSClock.obj
_OSMaskEventPend ./17k_slave_V0.02/app/grid.obj
_OSRdyMap ./17k_slave_V0.02/app/userisr.obj
_OSTCBCur ./17k_slave_V0.02/kernel/ports/OS_CPU_A.obj
_OSTCBHighRdy ./17k_slave_V0.02/kernel/ports/OS_CPU_A.obj
_OSTCBTbl ./17k_slave_V0.02/app/eeprom.obj
_OSTimerTick ./17k_slave_V0.02/app/OSClock.obj
_PieCtrlRegs ./17k_slave_V0.02/app/userisr.obj
_SciaRegs ./17k_slave_V0.02/cpu/SCI_Boot.obj
_SpiaRegs ./17k_slave_V0.02/app/spitask.obj
_SysCtrlRegs ./17k_slave_V0.02/cpu/SCI_Boot.obj

error #10234-D: unresolved symbols remain
error #10010: errors encountered during linking; "test2.out" not built

>> Compilation failure
makefile:187: recipe for target

/*
// TI File $Revision: /main/10 $
// Checkin $Date: April 15, 2009   09:57:22 $
//###########################################################################
//
// FILE:    28332_RAM_lnk.cmd
//
// TITLE:   Linker Command File For 28332 examples that run out of RAM
//
//          This ONLY includes all SARAM blocks on the 28332 device.
//          This does not include flash or OTP.
//
//          Keep in mind that L0 and L1 are protected by the code
//          security module.
//
//          What this means is in most cases you will want to move to
//          another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release:   $
// $Release Date:   $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map                                    */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
   library search path under project->build options, linker tab,
   library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28332
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections
   Notes:
         Memory blocks on F28332 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.
         L0/L1/L2 and L3 memory blocks are mirrored - that is
         they can be accessed in high memory or low memory.
         For simplicity only one instance is used in this
         linker file.
         Contiguous SARAM memory blocks can be combined
         if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode      */
   BEGIN      : origin = 0x000000, length = 0x000002     /* Boot to M0 will go here                      */
   RAMM0      : origin = 0x000050, length = 0x0003B0
   RAML0      : origin = 0x008000, length = 0x001000
   RAML1      : origin = 0x009000, length = 0x001000
   RAML2      : origin = 0x00A000, length = 0x001000
   RAML3      : origin = 0x00B000, length = 0x001000
   ZONE7A     : origin = 0x200000, length = 0x00FC00     /* XINTF zone 7 - program space */
   CSM_RSVD   : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   CSM_PWL    : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA            */
   ADC_CAL    : origin = 0x380080, length = 0x000009
   RESET      : origin = 0x3FFFC0, length = 0x000002
   IQTABLES   : origin = 0x3FE000, length = 0x000b50
   IQTABLES2  : origin = 0x3FEB50, length = 0x00008c
   FPUTABLES  : origin = 0x3FEBDC, length = 0x0006A0
   BOOTROM    : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
   /* BOOT_RSVD is used by the boot ROM for stack.               */
   /* This section is only reserved to keep the BOOT ROM from    */
   /* corrupting this area during the debug process              */
   BOOT_RSVD  : origin = 0x000002, length = 0x00004E     /* Part of M0, BOOT rom will use this for stack */
   RAMM1      : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML4      : origin = 0x00C000, length = 0x001000
   RAML5      : origin = 0x00D000, length = 0x001000
   ZONE7B     : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
}
SECTIONS
{
   /* Setup for "boot to SARAM" mode:
      The codestart section (found in DSP28_CodeStartBranch.asm)
      re-directs execution to the start of user code.  */
   codestart        : > BEGIN,     PAGE = 0
   
#ifdef __TI_COMPILER_VERSION__
   #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} > RAML0,      PAGE = 0
   #else
   ramfuncs         : > RAML0,     PAGE = 0   
   #endif
#endif    
   
   .text            : > RAML1,     PAGE = 0
   .cinit           : > RAML0,     PAGE = 0
   .pinit           : > RAML0,     PAGE = 0
   .switch          : > RAML0,     PAGE = 0
   .stack           : > RAMM1,     PAGE = 1
   .ebss            : > RAML4,     PAGE = 1
   .econst          : > RAML5,     PAGE = 1
   .esysmem         : > RAMM1,     PAGE = 1
   IQmath           : > RAML1,     PAGE = 0
   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD
   /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {
              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
   }
   */
   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
   DMARAML4         : > RAML4,     PAGE = 1
   DMARAML5         : > RAML5,     PAGE = 1
   ZONE7DATA        : > ZONE7B,    PAGE = 1
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used                    */
   csm_rsvd         : > CSM_RSVD   PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
   csmpasswds       : > CSM_PWL    PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

'test2.out' failed
gmake[1]: *** [test2.out] Error 1
makefile:183: recipe for target 'all' failed
gmake: *** [all] Error 2

**** Build Finished ****