The master clock appears on the SCL pin when the I2C module is configured to be a master on the
I2C-bus. This clock controls the timing of communication between the I2C module and a slave. As shown
in Figure 3, a second clock divider in the I2C module divides down the module clock to produce the
master clock. The clock divider uses the ICCL value of I2CCLKL to divide down the low portion of the
module clock signal and uses the ICCH value of I2CCLKH to divide down the high portion of the module
clock signal. See section Section 5.7.1 for the master clock frequency equation.
datasheet 上红色阴影的那句意思是不是 I2C模块初始化后， I2caRegs.I2CMDR.bit.MST=1;配置这个后SCL线上有波产生？
