When SCI Transmit FIFO is empty, how long does the FIFO interrupt actives？

I'm using F28035，enable SCI Transmit FIFO interrupt (TXFFIENA=1), and set TXFFIL=0 (Transmit FIFO interrupt level bits). 

Some times when run into Transmit FIFO interrupt ISR, I get no data to write to the TX FIFO ( thus the TX FIFO is empty for a long time), and I find the ISR will active continuously (this mode works for me), but I do not know how long does the interrupts active between one from another?