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#ifdef _STANDALONE
#ifdef _FLASH
// Send boot command to allow the CPU02 application to begin execution
IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);
#else
// Send boot command to allow the CPU02 application to begin execution
IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_RAM);
#endif
#endif
When a particular GSx RAM block is owned by the CPU1 subsystem, CPU1 and CPU1.DMA have full access to that RAM block, whereas CPU2 and CPU2.DMA have only read access to it (no fetch/write access).
Master select and access protection configuration for each GSx RAM block can be individually locked by the user to prevent further update to these bit fields. The user can also choose to permanently lock the configuration to individual bit fields by setting the specific bit fields in the GSxCOMMIT register (refer to the register description for more details). Once configuration is committed for a particular GSx RAM block,
it can not be changed further until CPUx.SYSRS is issued. Only the CPU1 SW can change the master select configuration by writing into the GSxMSEL register, mapped on the CPU1. The GSxMSEL register, which is mapped to the CPU2 subsystem, is a status register which can only be used by CPU2 SW to know the master ownership for each GSx RAM block.
您好，我把GSxMSEL寄存器的低16位全部置为1，然后问题解决了，谢谢您的指导，但还有一点疑问：RM的3.11.1.3 Global Shared RAM (GSx RAM)里面有这样一句话：Emulation/Debugger access is allowed from both the CPUs, irrespective of the GSxMSEL
setting.我理解的是在仿真模式下，两个cpu均可以对GSxRAM进行读写操作，我现在就是在仿真模式下，为啥还得对GSxMSEL寄存器进行操作？谢谢！
