28335 MCBSP通讯问题

void InitMcbspa(void)
{
// McBSP-A register settings

McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
McbspaRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode.


McbspaRegs.MFFINT.all=0x0; // Disable all interrupts
McbspaRegs.RCR1.all=0x0;
McbspaRegs.RCR2.all=0x05;
// McbspaRegs.RCR1.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive)
// McbspaRegs.RCR1.bit.RFRLEN1=4;

McbspaRegs.XCR1.all=0x0;
McbspaRegs.XCR2.all=0x05;

// Single-phase frame, 1 word/frame, No companding (Transmit)
// McbspaRegs.XCR1.bit.XFRLEN1=4;

McbspaRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source
McbspaRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source
McbspaRegs.SRGR1.all = 0xff04; //
McbspaRegs.SRGR2.all = 0xA000; //
// McbspaRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
//McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods

//McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period
// McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;// CLKG frequency = LSPCLK/(CLKGDV+1)
McbspaRegs.MFFINT.bit.RINT = 1;

delay_loop(); // Wait at least 2 SRG clock cycles

McbspaRegs.SPCR2.bit.GRST=1;
McbspaRegs.SPCR1.bit.RINTM=0; //中断由RRDY产生// Enable the sample rate generator
clkg_delay_loop(); // Wait at least 2 CLKG cycles
McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset

}

检查一下你的接收管脚的gpio muxing配置正确吗？
当接收到一个中断时，状态标志位（像spcr1中的那些）处于什么状态？它们与回环模式运行时有什么不同吗？