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DSP28075的个GPIO配置问题

user5770074
Intellectual 330 points


采用芯片，DSP28075，当把GPIO外设配置成SPI时，为什么需要将采样窗的限定改为不同步及采样窗限定。也就是为什么GPxQSEL1/2 = 3；在我们实际使用过程中，我们把GPBQSEL2.Bit.GPIO54-57均设置成0，与SYSCLKOUT同步时，采用SPI时钟CLOCK POLARITY:0 CLOCK PHASE:1。根据手册，SPI应该在上升沿前半个周期发送数据，上升沿接收数据，通过示波器看到的结果为，SPI在上升沿时发送数据，导致接收端有数据错误，当把GPBQSEL2.Bit.GPIO54-57均设置成3.就不会出现这样的情况。为什么将GPIO配置成外设时，需要将GPxQSEL1/2寄存器设置为3

  • 0
    TI__Guru** 101655 points
    GPIO配置SPI的时候，对GPxQSEL的设置可以参考芯片技术手册2088页
    17.2.2 Configuring Device Pins
    The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
    glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
    GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
    Some IO functionality is defined by GPIO register settings independent of this peripheral. For input
    signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
    GPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.
    See the GPIO chapter for more details on GPIO mux and settings.