你们好：
我在使用一个28335平台的工程的时候，发现里面有一个InitFlash函数，使用了FlashRegs寄存器进行配置。
现在我想把这一工程转移到28379平台上来，但是我发现28379平台并不支持这一寄存器的配置，请问，我应该怎么配置呢？
有哪些文档介绍了28335以及28379平台的flash初始化功能？
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你们好：
我在使用一个28335平台的工程的时候，发现里面有一个InitFlash函数，使用了FlashRegs寄存器进行配置。
现在我想把这一工程转移到28379平台上来，但是我发现28379平台并不支持这一寄存器的配置，请问，我应该怎么配置呢？
有哪些文档介绍了28335以及28379平台的flash初始化功能？
有参考例程中的配置吗？F28379的flash配置比F28335的复杂很多，例程中对这个函数说明的挺清楚的，你可以参考一下：
void InitFlash(void)
{
EALLOW;
//
// The default value of VREADST is good enough for the flash to power up
// properly at the INTOSC frequency. Below VREADST configuration covers up
// to the max frequency possible for this device. This is required for
// proper flash wake up at the higher frequencies if users put it to sleep
// for power saving reason.
//
Flash0CtrlRegs.FBAC.bit.VREADST = 0x14;
//
// At reset bank and pump are in sleep. A Flash access will power up the
// bank and pump automatically.
//
// After a Flash access, bank and pump go to low power mode (configurable
// in FBFALLBACK/FPAC1 registers) if there is no further access to flash.
//
// Power up Flash bank and pump. This also sets the fall back mode of
// flash and pump as active.
//
Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1;
Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3;
//
// Disable Cache and prefetch mechanism before changing wait states
//
Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0;
Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0;
//
// Set waitstates according to frequency
//
// *CAUTION*
// Minimum waitstates required for the flash operating at a given CPU rate
// must be characterized by TI. Refer to the datasheet for the latest
// information.
//
#if CPU_FRQ_200MHZ
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3;
#endif
#if CPU_FRQ_150MHZ
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;
#endif
#if CPU_FRQ_120MHZ
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;
#endif
//
// Enable Cache and prefetch mechanism to improve performance of code
// executed from Flash.
//
Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1;
Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1;
//
// At reset, ECC is enabled. If it is disabled by application software and
// if application again wants to enable ECC.
//
Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;
EDIS;
//
// Force a pipeline flush to ensure that the write to the last register
// configured occurs before returning.
//
__asm(" RPT #7 || NOP");
}
//
// FlashOff - This function powers down the flash
//
// *CAUTION*
// This function MUST be executed out of RAM. Executing it out of OTP/Flash
// will yield unpredictable results. Also you must seize the flash pump in
// order to power it down.void InitFlash(void)
{
EALLOW;
//
// The default value of VREADST is good enough for the flash to power up
// properly at the INTOSC frequency. Below VREADST configuration covers up
// to the max frequency possible for this device. This is required for
// proper flash wake up at the higher frequencies if users put it to sleep
// for power saving reason.
//
Flash0CtrlRegs.FBAC.bit.VREADST = 0x14;
//
// At reset bank and pump are in sleep. A Flash access will power up the
// bank and pump automatically.
//
// After a Flash access, bank and pump go to low power mode (configurable
// in FBFALLBACK/FPAC1 registers) if there is no further access to flash.
//
// Power up Flash bank and pump. This also sets the fall back mode of
// flash and pump as active.
//
Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1;
Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3;
//
// Disable Cache and prefetch mechanism before changing wait states
//
Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0;
Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0;
//
// Set waitstates according to frequency
//
// *CAUTION*
// Minimum waitstates required for the flash operating at a given CPU rate
// must be characterized by TI. Refer to the datasheet for the latest
// information.
//
#if CPU_FRQ_200MHZ
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3;
#endif
#if CPU_FRQ_150MHZ
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;
#endif
#if CPU_FRQ_120MHZ
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;
#endif
//
// Enable Cache and prefetch mechanism to improve performance of code
// executed from Flash.
//
Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1;
Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1;
//
// At reset, ECC is enabled. If it is disabled by application software and
// if application again wants to enable ECC.
//
Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;
EDIS;
//
// Force a pipeline flush to ensure that the write to the last register
// configured occurs before returning.
//
__asm(" RPT #7 || NOP");
}
//
// FlashOff - This function powers down the flash
//
// *CAUTION*
// This function MUST be executed out of RAM. Executing it out of OTP/Flash
// will yield unpredictable results. Also you must seize the flash pump in
// order to power it down.