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The VREGENZ pin must be tied to VDDIO and an external source used to supply 1.2 V to VDD. During the ramp, VDD should be kept no more than 0.3 V above VDDIO.
There is an internal 12.8-mA current source from VDD3VFL to VDD when the flash banks are active. When the flash banks are active and the device is in a low-activity state (for example, a low-power mode), this internal current source can cause VDD to rise to approximately 1.3 V.
