28062pwm触发AD中断

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配置的是20K的AD中断，当把 AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 1; AdcRegs.INTSEL1N2.bit.INT1SEL = 15;

AD中断变为270多k, 当把 AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 0;时 AdcRegs.INTSEL1N2.bit.INT1SEL = 15;

这时AD中断为20k,请问什么原因

InitAdc();

EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT1 = &adc_isr;
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; //ADCINT1 trips after AdcResults latch
AdcRegs.INTSEL1N2.bit.INT1E = 1; //Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 0; //Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 15;
EDIS;

PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT 1.1 in the PIE
IER |= M_INT1;

EALLOW;
AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 1;

    AdcRegs.ADCSOC0CTL.bit.CHSEL = 0; //set SOC0 channel select to ADCINA0 UPS电压A
AdcRegs.ADCSOC1CTL.bit.CHSEL = 1; //set SOC1 channel select to ADCINA1 UPS电压B
AdcRegs.ADCSOC2CTL.bit.CHSEL = 2; //set SOC1 channel select to ADCINA2 UPS电压C
AdcRegs.ADCSOC3CTL.bit.CHSEL = 3; //set SOC1 channel select to ADCINA3 电网电压A
AdcRegs.ADCSOC4CTL.bit.CHSEL = 4; //set SOC1 channel select to ADCINA4 电网电压B
AdcRegs.ADCSOC5CTL.bit.CHSEL = 5; //set SOC1 channel select to ADCINA5 电网电压C
AdcRegs.ADCSOC6CTL.bit.CHSEL = 6; //set SOC1 channel select to ADCINA6 电网电流A
AdcRegs.ADCSOC7CTL.bit.CHSEL = 7; //set SOC0 channel select to ADCINA7 电网电流B
    AdcRegs.ADCSOC8CTL.bit.CHSEL = 8; //set SOC1 channel select to ADCINB0 电网电流C
AdcRegs.ADCSOC9CTL.bit.CHSEL = 9; //set SOC1 channel select to ADCINB1 电池电压
AdcRegs.ADCSOC10CTL.bit.CHSEL = 10; //set SOC1 channel select to ADCINB2 1.5V基准
AdcRegs.ADCSOC11CTL.bit.CHSEL = 11;
AdcRegs.ADCSOC12CTL.bit.CHSEL = 12;
AdcRegs.ADCSOC13CTL.bit.CHSEL = 13; //set SOC1 channel select to ADCINB2 1.5V基准
    AdcRegs.ADCSOC14CTL.bit.CHSEL = 14;
AdcRegs.ADCSOC15CTL.bit.CHSEL = 15;

AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 7; //set SOC0 start trigger on EPWM2A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 7; //set SOC1 start trigger on EPWM2A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 7; //set SOC2 start trigger on EPWM2A, due to round-robin SOC0 converts first then SOC1, then SOC2
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC6CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC7CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC8CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC9CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC10CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC11CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC12CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC13CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC14CTL.bit.TRIGSEL = 7;
AdcRegs.ADCSOC15CTL.bit.TRIGSEL = 7;

AdcRegs.ADCSOC0CTL.bit.ACQPS = 6; //set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6; //set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC2CTL.bit.ACQPS = 6; //set SOC2 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC3CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC4CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC5CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC6CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC7CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC8CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC9CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC10CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC11CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC12CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC13CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC14CTL.bit.ACQPS = 6;
AdcRegs.ADCSOC15CTL.bit.ACQPS = 6;

GpioCtrlRegs.GPAMUX2.bit.GPIO21= 0;
GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
EDIS;

EPwm2Regs.ETSEL.bit.SOCAEN = 1;        // Enable SOC on A group
    EPwm2Regs.ETSEL.bit.SOCASEL = ET_CTR_PRD;
    EPwm2Regs.ETPS.bit.SOCAPRD = ET_1ST;   // Generate pulse on 1st event
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm2Regs.CMPA.half.CMPA = 500; // Set compare A value
    EPwm2Regs.TBPRD       = 2250; // Set period for ePWM1
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;  // count up and start

5 年多前