我现在TMS320F28377S的配置如下：
1、CMPSS的配置：
void sInitCMPSS(void)
{
EALLOW;
//
//Enable CMPSS
//
Cmpss1Regs.COMPCTL.bit.COMPDACE = 1;
//
//NEG signal comes from DAC
//
Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = 0;
Cmpss1Regs.COMPCTL.bit.COMPLSOURCE = 0;
// COMP-H-L output is NOT inverted
Cmpss1Regs.COMPCTL.bit.COMPHINV = 0;
Cmpss1Regs.COMPCTL.bit.COMPLINV = 0;
//Disable aynch COMP-H-L ouput
Cmpss1Regs.COMPCTL.bit.ASYNCHEN = 0;
Cmpss1Regs.COMPCTL.bit.ASYNCLEN = 0;
// Configure CTRIPOUT path
// Digital filter output feeds CTRIPH and CTRIPOUTH
//
// High comparator CTRIPH source select.
//0 Asynchronous comparator output drives CTRIPH
//1 Synchronous comparator output drives CTRIPH
// 2 Output of digital filter drives CTRIPH
//3 Latched output of digital filter drives CTRIPH
Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = 1;
Cmpss1Regs.COMPCTL.bit.CTRIPLSEL = 1;
// Set up COMPHYSCTL register
Cmpss1Regs.COMPHYSCTL.bit.COMPHYS = 0; //Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs.
//0 None
//1 Set to typical hysteresis
//2 Set to 2x of typical hysteresis
//3 Set to 3x of typical hysteresis
//4 Set to 4x of typical hysteresis
//Use VDDA as the reference for DAC
Cmpss1Regs.COMPDACCTL.bit.SELREF = 0;
Cmpss1Regs.COMPDACCTL.bit.SWLOADSEL = 1; //Software load select. Determines whether DACxVALA is updated
//from DACxVALS on SYSCLK or EPWMSYNCPER.
//0 DACxVALA is updated from DACxVALS on SYSCLK
//1 DACxVALA is updated from DACxVALS on EPWMSYNCPER
//Reset type: SYSRSn
Cmpss1Regs.COMPDACCTL.bit.DACSOURCE = 0; // Ramp bypassed
// Load DACs - High and Low
Cmpss1Regs.DACHVALS.bit.DACVAL = 1172;
Cmpss1Regs.DACLVALS.bit.DACVAL = 1172;
//
// Configure Digital Filter
//Maximum CLKPRESCALE value provides the most time between samples,1MHZ
//
Cmpss1Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 0xC7;//samples = SAMPWIN + 1, threshold = THRESH + 1
//and prescale =CLKPRESCALE + 1.
Cmpss1Regs.CTRIPLFILCLKCTL.bit.CLKPRESCALE = 0xC7;
//
//Maximum SAMPWIN value provides largest number of samples
//
Cmpss1Regs.CTRIPHFILCTL.bit.SAMPWIN = 0x1F;
Cmpss1Regs.CTRIPLFILCTL.bit.SAMPWIN = 0x1F;
//
//Maximum THRESH value requires static value for entire window
// THRESH should be GREATER than half of SAMPWIN
//
Cmpss1Regs.CTRIPHFILCTL.bit.THRESH = 0x1F;
Cmpss1Regs.CTRIPLFILCTL.bit.THRESH = 0x1F;
//
//Reset filter logic & start filtering,Initialize all samples to the filter input value
//
Cmpss1Regs.CTRIPHFILCTL.bit.FILINIT = 1;
Cmpss1Regs.CTRIPLFILCTL.bit.FILINIT = 1;
//
// Clear the status register for latched comparator events
Cmpss1Regs.COMPSTSCLR.bit.HLATCHCLR = 1;
Cmpss1Regs.COMPSTSCLR.bit.LLATCHCLR = 1;
// Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch
Cmpss1Regs.COMPSTSCLR.bit.HSYNCCLREN = 1;
Cmpss1Regs.COMPSTSCLR.bit.LSYNCCLREN = 1;
// Configure CTRIPOUTH output pin
// Configure OUTPUTXBAR1 to be CTRIPOUT1H
//
OutputXbarRegs.OUTPUT1MUX0TO15CFG.bit.MUX0 = 1;
//
//Enable OUTPUTXBAR1 Mux for Output
//
OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX0 = 1;
EDIS;
}
2、PWM2的配置如下：
void sinitEPWM2(void)
{
EALLOW;
// Clear everything first
EPwmXbarRegs.TRIP4MUX0TO15CFG.all = 0x0000;
EPwmXbarRegs.TRIP4MUX16TO31CFG.all = 0x0000;
// Enable Muxes for ored input of CMPSS1H and 1L, i.e. .1 mux for Mux0
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 0; //cmpss1 - tripH
// Disable all the muxes first
EPwmXbarRegs.TRIP4MUXENABLE.all = 0x0000;
// Enable Mux 0 OR Mux 4 to generate TRIP4
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1;
//EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3; //Trip 4 is the input to the DCAHCOMPSEL
//EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL = 3; //Trip 4 is the input to the DCALCOMPSEL
EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 3; //Trip 4 is the input to the DCBHCOMPSEL
// EPwm2Regs.TZDCSEL.bit.DCAEVT1 = 2;//Digital Compare Output A Event 1 Selection
//000: Event disabled
//001: DCAH = low, DCAL = don't care
//010: DCAH = high, DCAL = don't care
//011: DCAL = low, DCAH = don't care
//100: DCAL = high, DCAH = don't care
//101: DCAL = high, DCAH = low
//110: Reserved
//111: Reserved
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = 2;
// EPwm2Regs.TZDCSEL.bit.DCBEVT1 = 2;
EPwm2Regs.TZDCSEL.bit.DCBEVT2 = 2;
EPwm2Regs.DCACTL.bit.EVT1SRCSEL = 0;//DCAEVT1 Source Signal Select
//0: Source Is DCAEVT1 Signal
//1: Source Is DCEVTFILT Signal
EPwm2Regs.DCACTL.bit.EVT2SRCSEL = 0;
EPwm2Regs.DCBCTL.bit.EVT1SRCSEL = 0;
EPwm2Regs.DCBCTL.bit.EVT2SRCSEL = 0;
// EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0;//DCAEVT1 Force Synchronization Signal Select
// //0: Source is synchronized with EPWMCLK
// //1: Source is passed through asynchronously
// EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0;
// EPwm2Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 0;
// EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 0;
// EPwm2Regs.DCACTL.bit.EVT1SOCE = 0;
// EPwm2Regs.DCACTL.bit.EVT1SYNCE = 0;
// EPwm2Regs.DCBCTL.bit.EVT1SOCE = 0;
// EPwm2Regs.DCBCTL.bit.EVT1SYNCE = 0;
EPwm2Regs.TZSEL.bit.CBC1 = 0;//Disable TZ1 as a CBC trip source for this ePWM module
EPwm2Regs.TZSEL.bit.CBC2 = 0;//Disable TZ2 as a CBC trip source for this ePWM module
EPwm2Regs.TZSEL.bit.CBC3 = 0;//Disable TZ3 as a CBC trip source for this ePWM module
EPwm2Regs.TZSEL.bit.CBC4 = 0;//Disable TZ4 as a CBC trip source for this ePWM module
EPwm2Regs.TZSEL.bit.CBC5 = 0;//Disable TZ5 as a CBC trip source for this ePWM module
EPwm2Regs.TZSEL.bit.CBC6 = 0;//Disable TZ6 as a CBC trip source for this ePWM module
EPwm2Regs.TZSEL.bit.OSHT1 = 0;//Disable TZ1 as a CBC trip source for this ePWM module
EPwm2Regs.TZSEL.bit.OSHT2 = 0;//Disable TZ2 as a CBC trip source for this ePWM module
EPwm2Regs.TZSEL.bit.OSHT3 = 0;//Disable TZ3 as a CBC trip source for this ePWM module
EPwm2Regs.TZSEL.bit.OSHT4 = 0;//Disable TZ4 as a CBC trip source for this ePWM module
EPwm2Regs.TZSEL.bit.OSHT5 = 0;//Disable TZ5 as a CBC trip source for this ePWM module
EPwm2Regs.TZSEL.bit.OSHT6 = 0;//Disable TZ6 as a CBC trip source for this ePWM module
EPwm2Regs.TZSEL.bit.DCAEVT1 = 0; //Digital Compare Output A Event 1 Select
// 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module.
// 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module.
EPwm2Regs.TZSEL.bit.DCBEVT1 = 0;
EPwm2Regs.TZSEL.bit.DCAEVT2 = 1; // Digital Compare Output A Event 2 Select
//0: Disable DCAEVT2 as a CBC trip source for this ePWM module
//1: Enable DCAEVT2 as a CBC trip source for this ePWM module
//Reset type: SYSRSn
EPwm2Regs.TZSEL.bit.DCBEVT2 = 1;
EDIS;
//--------------------------------------------------------------------------------//
EPwm2Regs.TBPRD = 1250; // Set timer period (12.5us)500=100M/80k/2
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
// EPwm2Regs.CMPA.bit.CMPA = 312;
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO = 2;//Action When TBCTR = 0
//Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.
//00: Do nothing (action disabled)
//01: Clear: force EPWMxA output low.
//10: Set: force EPWMxA output high.
//11: Toggle EPWMxA output: low output signal will be forced high,and a high signal will be forced low.
//Reset type: SYSRSn
EPwm2Regs.AQCTLB.bit.ZRO = 2;
// Set Dead-Band, set to a pair PWMAB
EPwm2Regs.DBCTL.bit.POLSEL = 0x2;//10: Active high complementary (AHC). EPWMxB is inverted..
EPwm2Regs.DBCTL.bit.IN_MODE = 0x0;
EPwm2Regs.DBCTL.bit.OUT_MODE = 0x3; //ensble DBM
// EPwm2Regs.DBCTL.bit.POLSEL = 0x2; //active high complementary mode
EPwm2Regs.DBRED.all = 50; //dead time is 0.5us=50*(1/100M)
EPwm2Regs.DBFED.all = 50; //dead time is 0.5us
// Set Trip-Zone
EALLOW;
// EPwm2Regs.TZCTL.bit.DCAEVT1 = 0x2; //Digital Compare Output A Event 1 Action On EPWMxA
// //00: High-impedance (EPWMxA = High-impedance state)
// //01: Force EPWMxA to a high state.
// //10: Force EPWMxA to a low state.
// //11: Do Nothing, trip action is disabled
// //Reset type: SYSRSn
// EPwm2Regs.TZCTL.bit.DCAEVT2 = 0x2;
// //EPwm2Regs.TZCTL.bit.DCBEVT1 = 0x2;
// //EPwm2Regs.TZCTL.bit.DCBEVT2 = 0x2;
// EPwm2Regs.TZCLR.bit.DCAEVT1 = 1;//Clear Flag for Digital Compare Output A Event 1
// //0: Writing 0 has no effect. This bit always reads back 0.
// //1: Writing 1 clears the DCAEVT1 event trip condition.
// //Reset type: SYSRSn
// EPwm2Regs.TZCLR.bit.DCAEVT2 = 1;
// EPwm2Regs.TZCLR.bit.DCBEVT1 = 1;
// EPwm2Regs.TZCLR.bit.DCBEVT2 = 1;
EPwm2Regs.TZCTL.bit.TZA = 2; //00: High-impedance (EPWMxA = High-impedance state)
//01: Force EPWMxA to a high state
//10: Force EPWMxA to a low state
//11: Do nothing, no action is taken on EPWMxA.
//Reset type: SYSRSn
EPwm2Regs.TZCTL.bit.TZB = 2;
EPwm2Regs.TZEINT.all = 0;
EDIS;
}
利用上面的配置，PWM2B引脚总是没有波形出来
