现使用Comparator Block做限流控制,设置如下
即Comparator2正端接ADCINA2,负端接内部DAC,将DCAEVT2和DCBEVT2 配制成CBC, 当ADCA2大于DAC时,则产生CBC事件,现在的问题是,当正端ADCINA2撤销后,PWM信号依旧封锁,并没有恢复,而限流希望信号撤销后PWM恢复,请问上面代码有什么问题吗
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shsizhong,
不好意思,说反了。
one-shot trip for major short circuits or over current conditions。
cycle-by-cycle trip for current limiting operation。
下面是对CBC的说明
The specified condition on the pins is automatically cleared when the ePWM time-base counter reaches zero (TBCTR = 0x0000) if the trip event is no longer present. Therefore, in this mode, the trip event is cleared or reset every PWM cycle. The TZFLG[CBC] flag bit will remain set until it is manually cleared by writing to the TZCLR[CBC] bit. If the cycle-by-cycle trip event is still present when the TZFLG[CBC] bit is cleared, then it will again be immediately set.
Eric