您好，我想把两路IO口相或后，作为trip源送入epwm中的DC子模块，用于产生DCAEVT1及DCBEVT1事件。
配置逻辑如下:1)GPIO16 GPIO17通过input-xabr选择为INPUT4 INPUT5
2)通过epwm-xabr将INPUT4 INPUT5 选为 TRIP4 TRIP5
3)通过配置DCALTRIPSEL DCBLTRIPSEL的TRIPINPUT4 TRIPINPUT5位(配成1)，将trip4 trip5选为组合的OR信号送入AL BL mux
4)配置DCTRIPSE的DCBLCOMPSEL DCALCOMPSEL位的数值为0xFF,即AL BL的输入源为组合信号
5)DCAEVT1 DCBEVT1发生条件是AL BL输入为low,发生DCAEVT1 DCBEVT1时将pwm引脚拉高
Epwm1Regs->DCALTRIPSEL.bit.TRIPINPUT4 = 1;
Epwm1Regs->DCALTRIPSEL.bit.TRIPINPUT5 = 1;
Epwm1Regs->DCBLTRIPSEL.bit.TRIPINPUT4 = 1;
Epwm1Regs->DCBLTRIPSEL.bit.TRIPINPUT5 = 1;
Epwm1Regs->DCTRIPSEL.bit.DCALCOMPSEL = DC_COMBINATION;
Epwm1Regs->DCTRIPSEL.bit.DCBLCOMPSEL = DC_COMBINATION;
Epwm1Regs->TZSEL.bit.DCAEVT1 = TZ_ENABLE;
Epwm1Regs->TZSEL.bit.DCBEVT1 = TZ_ENABLE;
Epwm1Regs->TZCTL.bit.TZA = TZ_FORCE_LOW;
Epwm1Regs->TZCTL.bit.TZB = TZ_FORCE_LOW;
目前测试时发现必须trip4 trip5同时为低才可以产生事件(这是"与"的逻辑)，我的理解是trip4 trip5是"相或"的逻辑，不应该其中一个为低，就可触发事件吗?
盼复，祝好!
