Other Parts Discussed in Thread: C2000WARE
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHE PAGE = 0, ALIGN(4)
.init_array : > FLASHE, PAGE = 0, ALIGN(4)
.text : >> FLASHB|FLASHC|FLASHD|FLASHE PAGE = 0, ALIGN(4)
codestart : > BEGIN PAGE = 0, ALIGN(4)
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.data : > RAMGS15 PAGE = 1
.bss : >> RAMGS3 PAGE = 1
.sysmem : > RAMGS2 PAGE = 1
/* Initalized sections go in Flash */
.const : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4)
.switch : > FLASHB PAGE = 0, ALIGN(4)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
GROUP
{
.TI.ramfunc
{
-l sfra_f32_tmu_eabi.lib
}
ramfuncs
} LOAD = FLASHD,
RUN = RAMGS0GS1,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
SFRA_F32_Data : > RAMGS2, ALIGN = 64, PAGE = 1
SFRA_Data : > RAMGS2, ALIGN = 64, PAGE=1
FPUmathTables : > FLASHN, PAGE = 0
.scratchpad : > RAMLS0LS1, PAGE = 1
.bss_cla : > RAMLS0LS1, PAGE = 1
controlVariables : > RAMLS0LS1, PAGE = 1
.const_cla : LOAD = FLASHH,
RUN = RAMLS2LS3LS4LS5,
RUN_START(Cla1ConstRunStart),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE(Cla1ConstLoadSize),
PAGE = 0
GROUP
{
isrcodefuncs
dclfuncs
} LOAD = FLASHH,
RUN = RAMLS2LS3LS4LS5,
LOAD_START(isrcodefuncsLoadStart),
LOAD_SIZE(isrcodefuncsLoadSize),
LOAD_END(isrcodefuncsLoadEnd),
RUN_START(isrcodefuncsRunStart),
RUN_SIZE(isrcodefuncsRunSize),
RUN_END(isrcodefuncsRunEnd),
PAGE = 0, ALIGN(4)
/* CLA specific sections */
Cla1Prog : LOAD = FLASHH,
RUN = RAMLS2LS3LS4LS5,
LOAD_START(Cla1ProgLoadStart),
RUN_START(Cla1ProgRunStart),
LOAD_SIZE(Cla1ProgLoadSize),
PAGE = 0, ALIGN(4)
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, PAGE = 1
MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, PAGE = 1
}

上面是CPU1的内存分布和调用IPC的例程,使用IPC_sendcommand可以设置寄存器,但是CPU2的IPC0中断无法启动