C28xx_CPU1: GEL Output:
Memory Map Initialization Complete
C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
C28xx_CPU1: Error during Flash Verification. Address 0x00082000, Expected 0x0000761B, Read 0x0000FFFF
C28xx_CPU1: File Loader: Memory write failed: Unknown error
C28xx_CPU1: GEL: File: D:\2023\1p_inverter\1P_280049\CPU1_FLASH\1P_280049.out: Load failed.
C28xx_CPU1: Error during Flash Verification. Address 0x00080000, Expected 0x00000048, Read 0x0000FFFF
C28xx_CPU1: Please make sure the memory location you are programming have not already been programmed.
C28xx_CPU1: Error during Flash Verification. Address 0x0008109C, Expected 0x00000000, Read 0x0000FFFF
C28xx_CPU1: Please make sure the memory location you are programming have not already been programmed.
C28xx_CPU1: Error during Flash Verification. Address 0x000841DC, Expected 0x00000072, Read 0x0000FFFF
C28xx_CPU1: Please make sure the memory location you are programming have not already been programmed.
我的CMD如下(除了合并5个小代码区，3个小数据区，都和例程一样的)：
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x0000F6, length = 0x00030A
RAMLS0_1_2_3_4 : origin = 0x008000, length = 0x002800 //TI原来是5个小代码区，此处合并了5个代码区
/*
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
*/
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
/* BANK 0 */
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE /* on-chip Flash */
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000 /* on-chip Flash */
/* BANK 1 */
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0 /* on-chip Flash */
// FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMLS5_6_7 : origin = 0x00A800, length = 0x001800
//RAMLS5 : origin = 0x00A800, length = 0x000800
//RAMLS6 : origin = 0x00B000, length = 0x000800
//RAMLS7 : origin = 0x00B800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x002000
RAMGS1 : origin = 0x00E000, length = 0x002000
RAMGS2 : origin = 0x010000, length = 0x002000
RAMGS3 : origin = 0x012000, length = 0x001FF8
// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0, ALIGN(4)
.text : >> FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3 | FLASH_BANK0_SEC5, PAGE = 0, ALIGN(4)
.cinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
.switch : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
.stack : > RAMM1, PAGE = 1
#if defined(__TI_EABI__)
.init_array : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
.bss : > RAMLS5_6_7, PAGE = 1
.bss:output : > RAMLS0_1_2_3_4, PAGE = 0
.bss:cio : > RAMLS0_1_2_3_4, PAGE = 0
.data : > RAMLS5_6_7, PAGE = 1
.sysmem : > RAMLS5_6_7, PAGE = 1
/* Initalized sections go in Flash */
.const : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
#else
.pinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
.ebss : > RAMLS5_6_7, PAGE = 1
.esysmem : > RAMLS5_6_7, PAGE = 1
.cio : > RAMLS0_1_2_3_4, PAGE = 0
.econst : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
#endif
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1
#if defined(__TI_EABI__)
.TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
RUN = RAMLS0_1_2_3_4,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#else
.TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
RUN = RAMLS0_1_2_3_4,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#endif
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
