void InitCMPSS(void)
{
//反向输入端配置
EALLOW;
Cmpss1Regs.COMPCTL.bit.COMPDACE = 1; //比较器DAC使能
Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = 0; //高侧比较器方向输入端为DAC
Cmpss1Regs.COMPCTL.bit.COMPHINV = 0; //比较器输出同向
Cmpss1Regs.COMPCTL.bit.ASYNCHEN = 0; //
Cmpss1Regs.COMPDACCTL.bit.DACSOURCE = 0; //DAC更新数据来自于其影子寄存器
Cmpss1Regs.COMPDACCTL.bit.SELREF = 0; //VDDA作为DAC的参考电压
Cmpss1Regs.COMPDACCTL.bit.SWLOADSEL = 0; //使用系统时钟同步DAC
//配置限流值
Cmpss1Regs.DACHVALS.bit.DACVAL = 2000; //配置DAC的影子寄存器值
/*数字滤波*/
Cmpss1Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 0x3FF;
Cmpss1Regs.CTRIPHFILCTL.bit.SAMPWIN = 31;
Cmpss1Regs.CTRIPHFILCTL.bit.THRESH = 31;
Cmpss1Regs.CTRIPHFILCTL.bit.FILINIT = 1;
Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = 0;
Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = 0; //比较器输出非同步非滤波信号
Cmpss1Regs.COMPHYSCTL.bit.COMPHYS = 4; //设置典型的滞环宽度
//同向输入端配置
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP1HPMXSEL = 0; //选择B6引脚作为高侧比较器1的同向输入端,B6端接的是PFC_Io，相当于是输出电流限流。就是输出不能大于一个值。
//选择EpwmXbar中的TRIP4通道中的MUX0.0，输出触发（过流）信号，输出TRIP4信号，触发DC模块。
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 0;//Select Bits for EPWM-XBAR TRIP4 Mux0：0.0
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1;//复用开关使能
EDIS;
}
void initEPWM(void)
{
EALLOW;
//--------------------PWM1 Initiation------------------------//
// Setup TBCLK
EPwm1Regs.TBPRD = 250; // Set timer period 频率为100M/500=200kHz
EPwm1Regs.TBPHS.bit.TBPHS= 0x0000; // Phase is 0设置初始相位，相对于时钟周期超前0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;///// TB_COUNT_UP
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading不使用外部同步时钟，加载相位寄存器
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUTEPWMCLK / (HSPCLKDIV x CLKDIV)
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
//EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm1Regs.CMPA.bit.CMPA = 125;//设置占空比50%
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
// Active Low PWMs - Setup Deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//DBCTL[OUT_MODE]
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
//EPwm1Regs.DBRED.bit.DBRED = 0;//0
//EPwm1Regs.DBFED.bit.DBFED = 0;//0
//Configure the HRPWM
EPwm1Regs.HRCNFG.bit.HRLOAD = 2; // Load on either CTR = Zero or CTR = PRD
EPwm1Regs.HRCNFG.bit.AUTOCONV = 1; // Enable auto-conversion
EPwm1Regs.HRCNFG.bit.EDGMODE = 0x11; // MEP control on both edges
EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1;
EPwm1Regs.HRPCTL.bit.HRPE = 1; // Enable high-resolution period control
//EPwm1Regs.TBPRDHR =
EPwm1Regs.CMPA.bit.CMPAHR = 0x0000;
//Epwm1 TZ Configuration
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3;//TRIPIN4 : DCAH
EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 3;//TRIPIN4 : DCBH
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 2;//Digital Compare Output A Event 1 Selection:DCAH = high, DCAL = don't care
EPwm1Regs.TZDCSEL.bit.DCBEVT1 = 2;//Digital Compare Output B Event 1 Selection:DCBH = high, DCBL = don't care
EPwm1Regs.TZSEL.bit.DCAEVT1 = 1;//Enable DCAEVT1 as a OST trip source for this ePWM module
EPwm1Regs.TZSEL.bit.DCBEVT1 = 1;//Enable DCBEVT1 as a OST trip source for this ePWM module
EPwm1Regs.TZCTL2.bit.ETZE = 0x01; //Use trip action defined in TZCTL2, TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored
EPwm1Regs.TZCTLDCA.bit.DCAEVT1U = 0x10;
EPwm1Regs.TZCTLDCA.bit.DCAEVT1D = 0x10;
EPwm1Regs.TZCTLDCB.bit.DCBEVT1U = 0x10;
EPwm1Regs.TZCTLDCB.bit.DCBEVT1D = 0x10;
//enable TZ interrupt
EPwm1Regs.TZEINT.bit.DCAEVT1 = 1;//Enable interrupt generation
//-----------------------PWM2 Initiation------------------------------//
// Setup TBCLK
EPwm2Regs.TBPRD = 250; // Set timer period 200kHz 频率为100M/500=200kHz
EPwm2Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;//TB_COUNT_UP_DOWN; // Count up down
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;//// Enable phase loading
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;////CTR = zero: Time-base counter equal to zero (TBCTR = 0x00)
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm2Regs.CMPA.bit.CMPA = 125;////49900;设置占空比为
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;///AQ_SET; ////
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; ////AQ_CLEAR;//// // Set PWM1A on Zero
// Active Low PWMs - Setup Deadband
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;//0x2:AHC 0x1:ALC 0:AH b通道不反转
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
//EPwm2Regs.DBRED.bit.DBRED = 0;//0
//EPwm2Regs.DBFED.bit.DBFED = 0;//0
//Configure the HRPWM
EPwm2Regs.HRCNFG.bit.HRLOAD = 2; // Load on either CTR = Zero or CTR = PRD
EPwm2Regs.HRCNFG.bit.AUTOCONV = 1; // Enable auto-conversion
EPwm2Regs.HRCNFG.bit.EDGMODE = 0x11; // MEP control on both edges
EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 1;
EPwm2Regs.HRPCTL.bit.HRPE = 1; // Enable high-resolution period control
//EPwm2Regs.TBPRDHR =
EPwm2Regs.CMPA.bit.CMPAHR = 0x0000;
//Epwm2 TZ Configuration
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3;//TRIPIN4 : DCAH
EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 3;//TRIPIN4 : DCBH
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = 2;//Digital Compare Output A Event 1 Selection:DCAH = high, DCAL = don't care
EPwm2Regs.TZDCSEL.bit.DCBEVT1 = 2;//Digital Compare Output B Event 1 Selection:DCBH = high, DCBL = don't care
EPwm2Regs.TZSEL.bit.DCAEVT1 = 1;//Enable DCAEVT1 as a OST trip source for this ePWM module
EPwm2Regs.TZSEL.bit.DCBEVT1 = 1;//Enable DCBEVT1 as a OST trip source for this ePWM module
EPwm2Regs.TZCTL2.bit.ETZE = 0x01; //Use trip action defined in TZCTL2, TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored
EPwm2Regs.TZCTLDCA.bit.DCAEVT1U = 0x10;
EPwm2Regs.TZCTLDCA.bit.DCAEVT1D = 0x10;
EPwm2Regs.TZCTLDCB.bit.DCBEVT1U = 0x10;
EPwm2Regs.TZCTLDCB.bit.DCBEVT1D = 0x10;
//-----------------------PWM3 Initiation------------------------------//
// Setup TBCLK
EPwm3Regs.TBPRD = 250; // Set timer period PWM 频率为100M/500=200kHz
EPwm3Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;//TB_COUNT_UP; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;//// TB_DISABLE;///// // Disable phase loading
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;////CTR = zero: Time-base counter equal to zero (TBCTR = 0x00)
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm3Regs.CMPA.bit.CMPA = 125;////49900;设置占空比为0.5
// Set actions
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;///AQ_SET; ////
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; ////AQ_CLEAR;//// // Set PWM1A on Zero
// Active Low PWMs - Setup Deadband
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;//0x2 0:AH b通道不反转
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBRED.bit.DBRED = 0;//0
EPwm3Regs.DBFED.bit.DBFED = 0;//0
//Configure the HRPWM
EPwm3Regs.HRCNFG.bit.HRLOAD = 2; // Load on either CTR = Zero or CTR = PRD
EPwm3Regs.HRCNFG.bit.AUTOCONV = 1; // Enable auto-conversion
EPwm3Regs.HRCNFG.bit.EDGMODE = 0x11; // MEP control on both edges
EPwm3Regs.HRPCTL.bit.TBPHSHRLOADE = 1;
EPwm3Regs.HRPCTL.bit.HRPE = 1; // Enable high-resolution period control
//EPwm3Regs.TBPRDHR =
EPwm3Regs.CMPA.bit.CMPAHR = 0x0000;
//Epwm3 TZ Configuration
EPwm3Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3;//TRIPIN4 : DCAH
EPwm3Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 3;//TRIPIN4 : DCBH
EPwm3Regs.TZDCSEL.bit.DCAEVT1 = 2;//Digital Compare Output A Event 1 Selection:DCAH = high, DCAL = don't care
EPwm3Regs.TZDCSEL.bit.DCBEVT1 = 2;//Digital Compare Output B Event 1 Selection:DCBH = high, DCBL = don't care
EPwm3Regs.TZSEL.bit.DCAEVT1 = 1;//Enable DCAEVT1 as a OST trip source for this ePWM module
EPwm3Regs.TZSEL.bit.DCBEVT1 = 1;//Enable DCBEVT1 as a OST trip source for this ePWM module
EPwm3Regs.TZCTL2.bit.ETZE = 0x01; //Use trip action defined in TZCTL2, TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored
EPwm3Regs.TZCTLDCA.bit.DCAEVT1U = 0x10;
EPwm3Regs.TZCTLDCA.bit.DCAEVT1D = 0x10;
EPwm3Regs.TZCTLDCB.bit.DCBEVT1U = 0x10;
EPwm3Regs.TZCTLDCB.bit.DCBEVT1D = 0x10;
//-----------------------PWM4 Initiation------------------------------//
// Setup TBCLK
EPwm4Regs.TBPRD = 25000; // Set timer period 2kHz
EPwm4Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm4Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;//TB_COUNT_UPDOWN
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;//// TB_DISABLE;///// // Disable phase loading
SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN = 0;//epwm4时钟与epwm1同步
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;//TB_SYNC_DISABLE;////CTR = zero: Time-base counter equal to zero (TBCTR = 0x00)
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm4Regs.CMPA.bit.CMPA = 250;//设置占空比为0.5
// Set actions
EPwm4Regs.AQCTLA.bit.CAU = AQ_SET;///AQ_SET; ////
EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR; ////AQ_CLEAR;//// // Set PWM1A on Zero
// Active Low PWMs - Setup Deadband
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;//0x2 0:AH b通道不反转
EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm4Regs.DBRED.bit.DBRED = 0;//0
EPwm4Regs.DBFED.bit.DBFED = 0;//0
//Configure the epwmSOC
EPwm4Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm4Regs.ETSEL.bit.SOCASEL = 3; // Enable event time-base counter equal to zero or period
EPwm4Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
//Configure the HRPWM
EPwm4Regs.HRCNFG.bit.HRLOAD = 2; // Load on either CTR = Zero or CTR = PRD
EPwm4Regs.HRCNFG.bit.AUTOCONV = 1; // Enable auto-conversion
EPwm4Regs.HRCNFG.bit.EDGMODE = 0x11; // MEP control on both edges
EPwm4Regs.HRPCTL.bit.TBPHSHRLOADE = 1;
EPwm4Regs.HRPCTL.bit.HRPE = 1; // Enable high-resolution period control
//EPwm4Regs.TBPRDHR =
EPwm4Regs.CMPA.bit.CMPAHR = 0x0000;
EDIS;
}
