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SM320F2812: ECAN在selftest模型下正常,实际硬件环境下无法发送数据

Part Number: SM320F2812

初学DSP开发,目前在测试自己板卡上,DSP CAN通信是否正常。

现在,在selftest模型下,数据可以正常的发送/接收。但连到实际硬件环境上时,发送总是不成功,卡在

do
{
ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
} while(ECanaShadow.CANTA.bit.TA0 == 0 );

这段代码处。

另外,示波器测量DSP的CANTX引脚,没有信号输出。

在物理上连接一个USBCAN或者不连接时,都无法从CANTX引脚测量到信号。

请问,这中情况可能是什么问题了

  • 配置代码如下

    #include "DSP281x_Device.h" // DSP281x Headerfile Include File
    #include "DSP281x_Examples.h" // DSP281x Examples Include File

    extern void delay_loop();

    #define TXCOUNT 1000 // Transmission will take place (TXCOUNT) times..

    #define ENABLE_SELF_TEST 0

    // Globals for this example
    //long i_2;
    long loopcount_2 = 0;


    void enable_Interrupt_2(void);
    void config_ecana_2();

    interrupt void INTA_ISR_2(void);


    void main_test_CAN_2(void)
    {
    struct ECAN_REGS ECanaShadow;
    Uint32 value = 0;
    long i = 0;

    InitSysCtrl();


    DINT;

    InitPieCtrl();

    IER = 0x0000;
    IFR = 0x0000;

    InitPieVectTable();

    InitECan();
    config_ecana_2();
    enable_Interrupt_2();
    //ECanaMboxes.MBOX0.MSGID.all = 0x95555555; // Extended Identifier

    /* Begin transmitting */
    while (1)
    {
    for(i=0; i < TXCOUNT; i++)
    {
    ECanaMboxes.MBOX0.MDL.all = value++;
    ECanaMboxes.MBOX0.MDH.all = value;

    ECanaShadow.CANTRS.all = 0;
    ECanaShadow.CANTRS.bit.TRS0 = 1; // Set TRS for mailbox under test
    ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

    do
    {
    ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
    } while(ECanaShadow.CANTA.bit.TA0 == 0 ); // Wait for TA5 bit to be set..


    ECanaShadow.CANTA.all = 0;
    ECanaShadow.CANTA.bit.TA0 = 1; // Clear TA0
    ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;

    loopcount_2 ++;
    }

    value = 0;
    loopcount_2 = 0;
    delay_loop();
    }

    //asm(" ESTOP0"); // Stop here
    }

    void config_ecana_2()
    {
    struct ECAN_REGS ECanaShadow;

    ECanaMboxes.MBOX0.MSGID.all = 0x95555555;
    ECanaMboxes.MBOX1.MSGID.all = 0x10000;

    /* Configure Mailbox under test as a Transmit mailbox */
    // cana邮箱0设置为发送
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
    ECanaShadow.CANMD.bit.MD0 = 0;
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

    /* Enable Mailbox under test */

    ECanaShadow.CANME.all = ECanaRegs.CANME.all;
    ECanaShadow.CANME.bit.ME0 = 1;
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;

    /* Write to DLC field in Master Control reg */

    ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;

    ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0;
    ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0;

    //cana配置位接受邮箱 mail1为接收邮箱
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
    ECanaShadow.CANMD.bit.MD1 = 1;
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
    // 使能邮箱1
    ECanaShadow.CANME.all = ECanaRegs.CANME.all;
    ECanaShadow.CANME.bit.ME1 =1;
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;

    EALLOW;
    ECanaRegs.CANMIM.all = 0xFFFFFFFF;

    // 配置为self-test 模式
    // Configure the eCAN for self test mode
    // Enable the enhanced features of the eCAN.
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.STM = ENABLE_SELF_TEST; // Configure CAN for self-test mode
    ECanaShadow.CANMC.bit.SCB = 1; // eCAN mode (reqd to access 32 mailboxes)
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    EDIS;
    }

    void enable_Interrupt_2(void)
    {
    struct ECAN_REGS ECanaShadow;
    EALLOW;

    ECanaRegs.CANMIM.all = 0xFFFFFFFF;
    ECanaRegs.CANMIL.all = 0; // 邮箱中断将产生ECAN0INT
    ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
    ECanaRegs.CANGIM.bit.I0EN = 1;

    /*ECanaShadow.CANMIM.all=ECanaRegs.CANMIM.all;
    ECanaShadow.CANMIM.bit.MIM1=1;
    ECanaRegs.CANMIM.all=ECanaShadow.CANMIM.all;

    ECanaShadow.CANMIL.all = ECanaRegs.CANMIL.all;
    ECanaShadow.CANMIL.all = 0; // 1-32号邮箱中断在中断线0上产生
    ECanaRegs.CANMIL.all = ECanaShadow.CANMIL.all;

    ECanaShadow.CANGIM.all = ECanaRegs.CANGIM.all;
    ECanaShadow.CANGIM.bit.I0EN = 1 ; // 中断线0使能
    ECanaRegs.CANGIM.all = ECanaShadow.CANGIM.all;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.STM = 0; // 0-Normal
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;*/

    EDIS;

    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.ECAN0INTA = &INTA_ISR_2;//R-CAN1 接收后中断函数
    EDIS; // This is needed to disable write to EALLOW protected registers

    IER |=M_INT9;// 开CPU中断1~9(必须开放对应的CPU级中断口)

    PieCtrlRegs.PIECRTL.bit.ENPIE = 1; // Enable the PIE block
    PieCtrlRegs.PIEIER9.bit.INTx5=1; //R-CAN0 接收邮箱

    EINT;//开总中断
    ERTM;//使能实时中断(CPU级的)
    }

    interrupt void INTA_ISR_2(void)
    {
    Uint32 TestMbox1,TestMbox2,TestMbox3;
    if(ECanaRegs.CANRMP.bit.RMP1==1)//RX get after flag and int BOX1
    {
    ECanaRegs.CANRMP.bit.RMP1=1; //clear GMIF1
    TestMbox1 = ECanaMboxes.MBOX1.MDL.all;
    TestMbox2 = ECanaMboxes.MBOX1.MDH.all;
    TestMbox3 = ECanaMboxes.MBOX1.MSGID.all;//从外部接收邮箱1的ID,1为接收邮箱(CANMD)
    }
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

    }

    void InitECan(void)
    {

    /* Create a shadow register structure for the CAN control registers. This is
    needed, since only 32-bit access is allowed to these registers. 16-bit access
    to these registers could potentially corrupt the register contents or return
    false data. This is especially true while writing to/reading from a bit
    (or group of bits) among bits 16 - 31 */

    struct ECAN_REGS ECanaShadow;

    asm(" EALLOW");

    /* Configure eCAN pins for CAN operation using GPIO regs*/

    GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
    GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;

    // eCAN control registers require 32-bit access.
    // If you want to write to a single bit, the compiler may break this
    // access into a 16-bit access. One solution, that is presented here,
    // is to use a shadow register to force the 32-bit access.

    // Read the entire register into a shadow register. This access
    // will be 32-bits. Change the desired bit and copy the value back
    // to the eCAN register with a 32-bit write.

    /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

    /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
    // HECC mode also enables time-stamping feature

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.SCB = 1;
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    /* Initialize all bits of 'Master Control Field' to zero */
    // Some bits of MSGCTRL register may come up in an unknown state. For proper operation,
    // all bits (including reserved bits) of MSGCTRL must be initialized to zero

    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

    // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
    // as a matter of precaution.

    /* Clear all TAn bits */

    ECanaRegs.CANTA.all = 0xFFFFFFFF;

    /* Clear all RMPn bits */

    ECanaRegs.CANRMP.all = 0xFFFFFFFF;

    /* Clear all interrupt flag bits */

    ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
    ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

    /* Configure bit timing parameters */

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;

    // Wait until the CPU has been granted permission to change the configuration registers
    do
    {
    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..

    ECanaShadow.CANBTC.all = 0;
    ECanaShadow.CANBTC.bit.BRPREG = 9; // 1 Mbps @ 150 MHz SYSCLKOUT
    ECanaShadow.CANBTC.bit.TSEG2REG = 2;
    ECanaShadow.CANBTC.bit.TSEG1REG = 10;
    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;

    // Wait until the CPU no longer has permission to change the configuration registers
    do
    {
    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..

    /* Disable all Mailboxes */
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.

    ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
    }

  • 你好,请问具体是哪一行?你可以使用插入代码功能以免回复过长。

    #include "DSP281x_Device.h" // DSP281x Headerfile Include File
    #include "DSP281x_Examples.h" // DSP281x Examples Include File
    
    extern void delay_loop();
    
    #define TXCOUNT 1000 // Transmission will take place (TXCOUNT) times..
    
    #define ENABLE_SELF_TEST 0
    
    // Globals for this example
    //long i_2;
    long loopcount_2 = 0;
    
    
    void enable_Interrupt_2(void);
    void config_ecana_2();
    
    interrupt void INTA_ISR_2(void);
    
    
    void main_test_CAN_2(void)
    {
    struct ECAN_REGS ECanaShadow;
    Uint32 value = 0;
    long i = 0;
    
    InitSysCtrl();
    
    
    DINT;
    
    InitPieCtrl();
    
    IER = 0x0000;
    IFR = 0x0000;
    
    InitPieVectTable();
    
    InitECan();
    config_ecana_2();
    enable_Interrupt_2();
    //ECanaMboxes.MBOX0.MSGID.all = 0x95555555; // Extended Identifier
    
    /* Begin transmitting */
    while (1)
    {
    for(i=0; i < TXCOUNT; i++)
    {
    ECanaMboxes.MBOX0.MDL.all = value++;
    ECanaMboxes.MBOX0.MDH.all = value;
    
    ECanaShadow.CANTRS.all = 0;
    ECanaShadow.CANTRS.bit.TRS0 = 1; // Set TRS for mailbox under test
    ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;
    
    do
    {
    ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
    } while(ECanaShadow.CANTA.bit.TA0 == 0 ); // Wait for TA5 bit to be set..
    
    
    ECanaShadow.CANTA.all = 0;
    ECanaShadow.CANTA.bit.TA0 = 1; // Clear TA0
    ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;
    
    loopcount_2 ++;
    }
    
    value = 0;
    loopcount_2 = 0;
    delay_loop();
    }
    
    //asm(" ESTOP0"); // Stop here
    }
    
    void config_ecana_2()
    {
    struct ECAN_REGS ECanaShadow;
    
    ECanaMboxes.MBOX0.MSGID.all = 0x95555555;
    ECanaMboxes.MBOX1.MSGID.all = 0x10000;
    
    /* Configure Mailbox under test as a Transmit mailbox */
    // cana邮箱0设置为发送
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
    ECanaShadow.CANMD.bit.MD0 = 0;
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
    
    /* Enable Mailbox under test */
    
    ECanaShadow.CANME.all = ECanaRegs.CANME.all;
    ECanaShadow.CANME.bit.ME0 = 1;
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;
    
    /* Write to DLC field in Master Control reg */
    
    ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
    
    ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0;
    ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0;
    
    //cana配置位接受邮箱 mail1为接收邮箱
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
    ECanaShadow.CANMD.bit.MD1 = 1;
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
    // 使能邮箱1
    ECanaShadow.CANME.all = ECanaRegs.CANME.all;
    ECanaShadow.CANME.bit.ME1 =1;
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;
    
    EALLOW;
    ECanaRegs.CANMIM.all = 0xFFFFFFFF;
    
    // 配置为self-test 模式
    // Configure the eCAN for self test mode
    // Enable the enhanced features of the eCAN.
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.STM = ENABLE_SELF_TEST; // Configure CAN for self-test mode
    ECanaShadow.CANMC.bit.SCB = 1; // eCAN mode (reqd to access 32 mailboxes)
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
    
    EDIS;
    }
    
    void enable_Interrupt_2(void)
    {
    struct ECAN_REGS ECanaShadow;
    EALLOW;
    
    ECanaRegs.CANMIM.all = 0xFFFFFFFF;
    ECanaRegs.CANMIL.all = 0; // 邮箱中断将产生ECAN0INT
    ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
    ECanaRegs.CANGIM.bit.I0EN = 1;
    
    /*ECanaShadow.CANMIM.all=ECanaRegs.CANMIM.all;
    ECanaShadow.CANMIM.bit.MIM1=1;
    ECanaRegs.CANMIM.all=ECanaShadow.CANMIM.all;
    
    ECanaShadow.CANMIL.all = ECanaRegs.CANMIL.all;
    ECanaShadow.CANMIL.all = 0; // 1-32号邮箱中断在中断线0上产生
    ECanaRegs.CANMIL.all = ECanaShadow.CANMIL.all;
    
    ECanaShadow.CANGIM.all = ECanaRegs.CANGIM.all;
    ECanaShadow.CANGIM.bit.I0EN = 1 ; // 中断线0使能
    ECanaRegs.CANGIM.all = ECanaShadow.CANGIM.all;
    
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.STM = 0; // 0-Normal
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;*/
    
    EDIS;
    
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.ECAN0INTA = &INTA_ISR_2;//R-CAN1 接收后中断函数
    EDIS; // This is needed to disable write to EALLOW protected registers
    
    IER |=M_INT9;// 开CPU中断1~9(必须开放对应的CPU级中断口)
    
    PieCtrlRegs.PIECRTL.bit.ENPIE = 1; // Enable the PIE block
    PieCtrlRegs.PIEIER9.bit.INTx5=1; //R-CAN0 接收邮箱
    
    EINT;//开总中断
    ERTM;//使能实时中断(CPU级的)
    }
    
    interrupt void INTA_ISR_2(void)
    {
    Uint32 TestMbox1,TestMbox2,TestMbox3;
    if(ECanaRegs.CANRMP.bit.RMP1==1)//RX get after flag and int BOX1
    {
    ECanaRegs.CANRMP.bit.RMP1=1; //clear GMIF1
    TestMbox1 = ECanaMboxes.MBOX1.MDL.all;
    TestMbox2 = ECanaMboxes.MBOX1.MDH.all;
    TestMbox3 = ECanaMboxes.MBOX1.MSGID.all;//从外部接收邮箱1的ID,1为接收邮箱(CANMD)
    }
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
    
    }
    
    void InitECan(void)
    {
    
    /* Create a shadow register structure for the CAN control registers. This is
    needed, since only 32-bit access is allowed to these registers. 16-bit access
    to these registers could potentially corrupt the register contents or return
    false data. This is especially true while writing to/reading from a bit
    (or group of bits) among bits 16 - 31 */
    
    struct ECAN_REGS ECanaShadow;
    
    asm(" EALLOW");
    
    /* Configure eCAN pins for CAN operation using GPIO regs*/
    
    GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
    GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;
    
    // eCAN control registers require 32-bit access.
    // If you want to write to a single bit, the compiler may break this
    // access into a 16-bit access. One solution, that is presented here,
    // is to use a shadow register to force the 32-bit access.
    
    // Read the entire register into a shadow register. This access
    // will be 32-bits. Change the desired bit and copy the value back
    // to the eCAN register with a 32-bit write.
    
    /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
    
    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
    
    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
    
    /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
    // HECC mode also enables time-stamping feature
    
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.SCB = 1;
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
    
    /* Initialize all bits of 'Master Control Field' to zero */
    // Some bits of MSGCTRL register may come up in an unknown state. For proper operation,
    // all bits (including reserved bits) of MSGCTRL must be initialized to zero
    
    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
    
    // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
    // as a matter of precaution.
    
    /* Clear all TAn bits */
    
    ECanaRegs.CANTA.all = 0xFFFFFFFF;
    
    /* Clear all RMPn bits */
    
    ECanaRegs.CANRMP.all = 0xFFFFFFFF;
    
    /* Clear all interrupt flag bits */
    
    ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
    ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
    
    /* Configure bit timing parameters */
    
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
    
    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    
    // Wait until the CPU has been granted permission to change the configuration registers
    do
    {
    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
    
    ECanaShadow.CANBTC.all = 0;
    ECanaShadow.CANBTC.bit.BRPREG = 9; // 1 Mbps @ 150 MHz SYSCLKOUT
    ECanaShadow.CANBTC.bit.TSEG2REG = 2;
    ECanaShadow.CANBTC.bit.TSEG1REG = 10;
    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
    
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
    
    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    
    // Wait until the CPU no longer has permission to change the configuration registers
    do
    {
    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
    
    /* Disable all Mailboxes */
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    
    ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
    }

  • 问题解决了,是硬件问题