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TMS320F280049C: 配置CLB模块，实现EPWM的组合逻辑。写了初始化CLB的函数，但是一调用这个函数就会报错，显示“unresolved symbol _Clb1LogicCfgRegs, first referenced in ./main.obj”，就是所有的CLB相关寄存器都无法编译。推测是官方没有写它的寄存器映射，不知道要怎么办。

? ?
Prodigy 40 points

Part Number: TMS320F280049C
Other Parts Discussed in Thread: C2000WARE

void InitCLB1(void)

{
EALLOW;
//configure epwm1A and epwm1B to CLB1_INPUT2 and CLB1_INPUT3
//configure CLB_GP_REG[0] and CLB_GP_REG[1] to CLB1_INPUT0 and CLB1_INPUT1
Clb1LogicCtrlRegs.CLB_GP_REG.bit.REG = 0;//Configure the INPUT0 and INPUT1（中断里面就是改这个来改变）
Clb1LogicCtrlRegs.CLB_GLBL_MUX_SEL_1.bit.GLBL_MUX_SEL_IN_2 = 0;//INPUT2 = epwm1A
Clb1LogicCtrlRegs.CLB_GLBL_MUX_SEL_1.bit.GLBL_MUX_SEL_IN_3 = 2;//INPUT3 = epwm1B
Clb1LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_2 = 0;//connect the epwm1A to CLB_INPUT_2
Clb1LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_3 = 0;//connect the epwm1B to CLB_INPUT_3
Clb1LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_0 = 1;//Input comes from CLB_GP_REG[0]
Clb1LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_1 = 1;//Input comes from CLB_GP_REG[1]
Clb1LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_2 = 0;//Input comes from selected external input
Clb1LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_3 = 0;//Input comes from selected external input

//LUT4_0 configure
Clb1LogicCfgRegs.CLB_LUT4_IN0.bit.SEL_0 = 24;//LUT4_0 IN0 input source:External Input 0
Clb1LogicCfgRegs.CLB_LUT4_IN1.bit.SEL_0 = 25;//LUT4_0 IN1 input source:External Input 1
Clb1LogicCfgRegs.CLB_LUT4_IN2.bit.SEL_0 = 26;//LUT4_0 IN2 input source:External Input 2
Clb1LogicCfgRegs.CLB_LUT4_IN3.bit.SEL_0 = 27;//LUT4_0 IN3 input source:External Input 3
Clb1LogicCfgRegs.CLB_LUT4_FN1_0.bit.FN0 = 0;//通过例程在线仿真得到结果，布尔运算。
//LUT4_1 configure
Clb1LogicCfgRegs.CLB_LUT4_IN0.bit.SEL_1 = 24;//LUT4_1 IN0 input source:External Input 0
Clb1LogicCfgRegs.CLB_LUT4_IN1.bit.SEL_1 = 25;//LUT4_1 IN1 input source:External Input 1
Clb1LogicCfgRegs.CLB_LUT4_IN2.bit.SEL_1 = 26;//LUT4_1 IN2 input source:External Input 2
Clb1LogicCfgRegs.CLB_LUT4_IN3.bit.SEL_1 = 27;//LUT4_1 IN3 input source:External Input 3
Clb1LogicCfgRegs.CLB_LUT4_FN1_0.bit.FN1 = 0;//通过例程在线仿真得到结果，布尔运算。

//OUTPUT configure
//OUTPUT_LUT_0:epwm1A
//OUTPUT_LUT_2:epwm1B
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN0 = 7;//Select the LUT4_0 output as the INPUT0 for OUTPUT_LUT_0
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN1 = 0;//Select 0 as the INPUT1 for OUTPUT_LUT_0
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN2 = 0;//Select 0 as the INPUT2 for OUTPUT_LUT_0
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.FN = 0;//通过例程在线仿真得到结果，输出函数。
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.IN0 = 15;//Select the LUT4_1 output as the INPUT0 for OUTPUT_LUT_2
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.IN1 = 0;//Select 0 as the INPUT1 for OUTPUT_LUT_2
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.IN2 = 0;//Select 0 as the INPUT2 for OUTPUT_LUT_2
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.FN = 0;//通过例程在线仿真得到结果，输出函数。
Clb1LogicCtrlRegs.CLB_OUT_EN = 5;//enable OUTPUT0 and OUTPUT2 //5=101;
EDIS;
}
void InitCLB2(void)
{
EALLOW;
//configure epwm1A and epwm1B to CLB1_INPUT2 and CLB1_INPUT3
//configure CLB_GP_REG[0] and CLB_GP_REG[1] to CLB1_INPUT0 and CLB1_INPUT1
Clb2LogicCtrlRegs.CLB_GP_REG.bit.REG = 0;//Configure the INPUT0 and INPUT1（中断里面就是改这个来改变）
Clb2LogicCtrlRegs.CLB_GLBL_MUX_SEL_1.bit.GLBL_MUX_SEL_IN_2 = 16;//INPUT2 = epwm2A
Clb2LogicCtrlRegs.CLB_GLBL_MUX_SEL_1.bit.GLBL_MUX_SEL_IN_3 = 18;//INPUT3 = epwm2B
Clb2LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_2 = 0;//connect the epwm1A to CLB_INPUT_2
Clb2LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_3 = 0;//connect the epwm1B to CLB_INPUT_3
Clb2LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_0 = 1;//Input comes from CLB_GP_REG[0]
Clb2LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_1 = 1;//Input comes from CLB_GP_REG[1]
Clb2LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_2 = 0;//Input comes from selected external input
Clb2LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_3 = 0;//Input comes from selected external input

//LUT4_0 configure
Clb2LogicCfgRegs.CLB_LUT4_IN0.bit.SEL_0 = 24;//LUT4_0 IN0 input source:External Input 0
Clb2LogicCfgRegs.CLB_LUT4_IN1.bit.SEL_0 = 25;//LUT4_0 IN1 input source:External Input 1
Clb2LogicCfgRegs.CLB_LUT4_IN2.bit.SEL_0 = 26;//LUT4_0 IN2 input source:External Input 2
Clb2LogicCfgRegs.CLB_LUT4_IN3.bit.SEL_0 = 27;//LUT4_0 IN3 input source:External Input 3
Clb2LogicCfgRegs.CLB_LUT4_FN1_0.bit.FN0 = 0;//通过例程在线仿真得到结果，布尔运算。
//LUT4_1 configure
Clb2LogicCfgRegs.CLB_LUT4_IN0.bit.SEL_1 = 24;//LUT4_1 IN0 input source:External Input 0
Clb2LogicCfgRegs.CLB_LUT4_IN1.bit.SEL_1 = 25;//LUT4_1 IN1 input source:External Input 1
Clb2LogicCfgRegs.CLB_LUT4_IN2.bit.SEL_1 = 26;//LUT4_1 IN2 input source:External Input 2
Clb2LogicCfgRegs.CLB_LUT4_IN3.bit.SEL_1 = 27;//LUT4_1 IN3 input source:External Input 3
Clb2LogicCfgRegs.CLB_LUT4_FN1_0.bit.FN1 = 0;//通过例程在线仿真得到结果，布尔运算。

//OUTPUT configure
//OUTPUT_LUT_0:epwm2A
//OUTPUT_LUT_2:epwm2B
Clb2LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN0 = 7;//Select the LUT4_0 output as the INPUT0 for OUTPUT_LUT_0
Clb2LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN1 = 0;//Select 0 as the INPUT1 for OUTPUT_LUT_0
Clb2LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN2 = 0;//Select 0 as the INPUT2 for OUTPUT_LUT_0
Clb2LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.FN = 0;//通过例程在线仿真得到结果，输出函数。
Clb2LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.IN0 = 15;//Select the LUT4_1 output as the INPUT0 for OUTPUT_LUT_2
Clb2LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.IN1 = 0;//Select 0 as the INPUT1 for OUTPUT_LUT_2
Clb2LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.IN2 = 0;//Select 0 as the INPUT2 for OUTPUT_LUT_2
Clb2LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.FN = 0;//通过例程在线仿真得到结果，输出函数。
Clb2LogicCtrlRegs.CLB_OUT_EN = 5;//enable OUTPUT0 and OUTPUT2
EDIS;
}
void InitCLB3(void)
{
EALLOW;
//configure epwm1A and epwm1B to CLB1_INPUT2 and CLB1_INPUT3
//configure CLB_GP_REG[0] and CLB_GP_REG[1] to CLB1_INPUT0 and CLB1_INPUT1
Clb3LogicCtrlRegs.CLB_GP_REG.bit.REG = 0;//Configure the INPUT0 and INPUT1（中断里面就是改这个来改变）
Clb3LogicCtrlRegs.CLB_GLBL_MUX_SEL_1.bit.GLBL_MUX_SEL_IN_2 = 32;//INPUT2 = epwm3A
Clb3LogicCtrlRegs.CLB_GLBL_MUX_SEL_1.bit.GLBL_MUX_SEL_IN_3 = 34;//INPUT3 = epwm3B
Clb3LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_2 = 0;//connect the epwm3A to CLB_INPUT_2
Clb3LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_3 = 0;//connect the epwm3B to CLB_INPUT_3
Clb3LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_0 = 1;//Input comes from CLB_GP_REG[0]
Clb3LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_1 = 1;//Input comes from CLB_GP_REG[1]
Clb3LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_2 = 0;//Input comes from selected external input
Clb3LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_3 = 0;//Input comes from selected external input
//LUT4_0 configure
Clb3LogicCfgRegs.CLB_LUT4_IN0.bit.SEL_0 = 24;//LUT4_0 IN0 input source:External Input 0
Clb3LogicCfgRegs.CLB_LUT4_IN1.bit.SEL_0 = 25;//LUT4_0 IN1 input source:External Input 1
Clb3LogicCfgRegs.CLB_LUT4_IN2.bit.SEL_0 = 26;//LUT4_0 IN2 input source:External Input 2
Clb3LogicCfgRegs.CLB_LUT4_IN3.bit.SEL_0 = 27;//LUT4_0 IN3 input source:External Input 3
Clb3LogicCfgRegs.CLB_LUT4_FN1_0.bit.FN0 = 0;//通过例程在线仿真得到结果，布尔运算。
//LUT4_1 configure
Clb3LogicCfgRegs.CLB_LUT4_IN0.bit.SEL_1 = 24;//LUT4_1 IN0 input source:External Input 0
Clb3LogicCfgRegs.CLB_LUT4_IN1.bit.SEL_1 = 25;//LUT4_1 IN1 input source:External Input 1
Clb3LogicCfgRegs.CLB_LUT4_IN2.bit.SEL_1 = 26;//LUT4_1 IN2 input source:External Input 2
Clb3LogicCfgRegs.CLB_LUT4_IN3.bit.SEL_1 = 27;//LUT4_1 IN3 input source:External Input 3
Clb3LogicCfgRegs.CLB_LUT4_FN1_0.bit.FN1 = 0;//通过例程在线仿真得到结果，布尔运算。

//OUTPUT configure
//OUTPUT_LUT_0:epwm3A
//OUTPUT_LUT_2:epwm3B
Clb3LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN0 = 7;//Select the LUT4_0 output as the INPUT0 for OUTPUT_LUT_0
Clb3LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN1 = 0;//Select 0 as the INPUT1 for OUTPUT_LUT_0
Clb3LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN2 = 0;//Select 0 as the INPUT2 for OUTPUT_LUT_0
Clb3LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.FN = 0;//通过例程在线仿真得到结果，输出函数。
Clb3LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.IN0 = 15;//Select the LUT4_1 output as the INPUT0 for OUTPUT_LUT_2
Clb3LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.IN1 = 0;//Select 0 as the INPUT1 for OUTPUT_LUT_2
Clb3LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.IN2 = 0;//Select 0 as the INPUT2 for OUTPUT_LUT_2
Clb3LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.FN = 0;//通过例程在线仿真得到结果，输出函数。
Clb3LogicCtrlRegs.CLB_OUT_EN = 5;//enable OUTPUT0 and OUTPUT2
EDIS;
}

  • 0
    TI__Guru 65745 points

    我建议你在TI例程的基础上进行修改。

    目前TI有关这个器件的CLB例程只提供了driverlib版本，所以你说的这一点是有可能的：

    “推测是官方没有写它的寄存器映射”

    相关例程的路径：

    C:\ti\c2000\C2000Ware_4_03_00_00\driverlib\f28004x\examples\clb