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void InitFlash(void) { EALLOW; //Enable Flash Pipeline mode to improve performance //of code executed from Flash. FlashRegs.FOPT.bit.ENPIPE = 1;
// CAUTION //Minimum waitstates required for the flash operating //at a given CPU rate must be characterized by TI. //Refer to the datasheet for the latest information. #if CPU_FRQ_150MHZ //Set the Paged Waitstate for the Flash FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;
//Set the Random Waitstate for the Flash FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;
//Set the Waitstate for the OTP FlashRegs.FOTPWAIT.bit.OTPWAIT = 8; #endif
#if CPU_FRQ_100MHZ //Set the Paged Waitstate for the Flash FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;
//Set the Random Waitstate for the Flash FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;
//Set the Waitstate for the OTP FlashRegs.FOTPWAIT.bit.OTPWAIT = 5; #endif // CAUTION //ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; EDIS;
//Force a pipeline flush to ensure that the write to //the last register configured occurs before returning.
