This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
你好,专家。我在用McBSP作为SPI功能接收数据时, while(McbspaRegs.MFFRX.bit.RXFFST !=1 )此句不设置的话能够接收到数据(数据不对),可是如果设置上句的话就接收不到,利用的是FIFO功能,参考TI的例程
请问这是怎么回事
while(McbspaRegs.MFFRX.bit.RXFFST !=1的使用目的是确定McBsp中有收到数据。
楼主用的是281x系列芯片吧,请看一下下面的McBsp的user guide,里面2.3章有说要如何设置McBsp的相关寄存器.
此外也请楼主用示波器看一下时序。
你好,Forrest,我又看了usee guide,然后借了参考书也看了一下,感觉寄存器设置的没有问题啊。现在的情况是:
McbspaRegs.MFFRX.bit.RXFFST的数值始终为16,我看guide说这是代表可用16个字,可是正常的是不是应该为0吧?我把while(McbspaRegs.MFFRX.bit.RXFFST !=1改为while(McbspaRegs.MFFRX.bit.RXFFST !=16就能接收到数据(也不正确),我现在不知道怎么办了?能帮我一下吗?谢谢!!
RXFFST的值为16说明已经收到了数据,SPI有时钟和极性这需要注意一下,否则收到的数据会不正确。
while(McbspaRegs.MFFRX.bit.RXFFST ==0){};即可。你那里McBSP是主还是从?
此外也请楼主用示波器看一下时序。
我按照你说的,看它的时序了,时序现在没有问题。McBSP设为从,用来接收数据。我刚才查看寄存器McbspaRegs.MFFRX.bit.RXFFOVF_FLAG为1,即说是溢出了,是不是正常的话,此位应该为0啊?
我按照你说的,看它的时序了,时序现在没有问题。McBSP设为从,用来接收数据。我刚才查看寄存器McbspaRegs.MFFRX.bit.RXFFOVF_FLAG为1,即说是溢出了,是不是正常的话,此位应该为0啊?
是的应该为0.
我写了一个小程序:)。在2812上McBSP为从,SPI为主互相通信。
//########################################################################### // // FILE: Example_281xMCBSP__SPI_FFDLB.c // // TITLE: DSP281x Device McBSP in SPI mode Digital Loop Back program. // // ASSUMPTIONS: // // This program requires the DSP281x header files. // As supplied, this project is configured for "boot to H0" operation. // // Other then boot mode pin configuration, no other hardware configuration // is required. // // DESCRIPTION: // // Digital loopback tests for the McBSP peripheral in SPI master mode. // // Three different serial word sizes can be tested. // // Before compiling this project: // * Select the serial word size (8/16/32) by using // the #define statements at the beginning of the code. // // * Select the FIFO level by using the #define statement // at the beginning of the code. // // This example does not use interrupts. Instead a polling method // is used to check the level of the receive FIFO. The incoming // data is checked for accuracy. If an error is found the error() // function is called and execution stops. // // McBSP Signals SPI equivalent // ------------------------------------- // MCLKX SPICLK (master) // MFSX SPISTE (master) // MDX SPISIMO // MCLKR SPICLK (slave - not used for this example) // MFSR SPISTE (slave - not used for this example) // MDR SPISOMI (not used for this example) // // This program will execute and transmit words until terminated by the user. // // By default for the McBSP examples, the McBSP sample rate generator (SRG) input // clock frequency is LSPCLK (150E6/4) assuming SYSCLKOUT = 150 MHz. // If while testing, the SRG input frequency // is changed, the #define MCBSP_SRG_FREQ (150E6/4) in the Mcbsp.c file must // also be updated accordingly. This define is used to determine the Mcbsp initialization // delay after the SRG is enabled, which must be at least 2 SRG clock cycles. // // Watch Variables: // sdata1 // sdata2 // rdata1 // rdata2 // rdata1_point // rdata2_point // //########################################################################### // // Original Author: S.S. // // $TI Release: DSP281x C/C++ Header Files V1.20 $ // $Release Date: July 27, 2009 $ //########################################################################### #include "DSP281x_Device.h" // DSP281x Headerfile Include File #include "DSP281x_Examples.h" // DSP281x Examples Include File // Define the level of the FIFO 1-16 #define FIFO_LEVEL 1 // Prototype statements for functions found within this file. void init_mcbsp_spi(void); void mcbsp_fifo_init(void); void error(void); void spi_fifo_init(void); Uint16 sdata[8]; // Send data buffer Uint16 rdata[8]={0,0,0,0,0,0,0,0}; // Receive data buffer Uint16 rdataMC1[8]={0,0,0,0,0,0,0,0}; // Receive data buffer Uint16 rdataMC2[8]; // Receive data buffer Uint16 rdata_point; // Keep track of where we are // in the data stream to check received data // Global data for this example Uint16 sdata1 = 0x000; // Sent Data Uint16 rdata1 = 0x000; // Recieved Data Uint16 sdata2 = 0x000; // Sent Data Uint16 rdata2 = 0x000; // Recieved Data Uint16 rdata1_point; Uint16 rdata2_point; void main(void) { Uint16 i; // Step 1. Initialize System Control: // PLL, WatchDog, enable Peripheral Clocks // This example function is found in the DSP281x_SysCtrl.c file. InitSysCtrl(); // Step 2. Initalize GPIO: // This example function is found in the DSP281x_Gpio.c file and // illustrates how to set the GPIO to it's default state. // InitGpio(); // Skipped for this example // For this example, only enable the GPIO for McBSP InitMcbspGpio(); // Select GPIOs to be McBSP pins // Port F MUX - x011 1111 0000 0000 // Step 3. Clear all interrupts and initialize PIE vector table: // Disable CPU interrupts DINT; // Initialize PIE control registers to their default state. // The default state is all PIE interrupts disabled and flags // are cleared. // This function is found in the DSP281x_PieCtrl.c file. InitPieCtrl(); // Disable CPU interrupts and clear all CPU interrupt flags: IER = 0x0000; IFR = 0x0000; // Initialize the PIE vector table with pointers to the shell Interrupt // Service Routines (ISR). // This will populate the entire table, even if the interrupt // is not used in this example. This is useful for debug purposes. // The shell ISR routines are found in DSP281x_DefaultIsr.c. // This function is found in DSP281x_PieVect.c. InitPieVectTable(); // Step 4. Initialize all the Device Peripherals: // This function is found in DSP281x_InitPeripherals.c // InitPeripherals(); // Not required for this example mcbsp_fifo_init(); // Initialize the Mcbsp FIFO init_mcbsp_spi(); // Initalize the Mcbsp in spi master loopback mode spi_fifo_init(); // Initialize the SPI only // Step 5. User specific code, enable interrupts: // Initalize the send data buffer sdata[0] = 0x1111; sdata[1] = 0x2222; sdata[2] = 0x3333; sdata[3] = 0x4444; sdata[4] = 0x5555; sdata[5] = 0x6666; sdata[6] = 0x7777; sdata[7] = 0x8888; rdataMC2[0] = 0x1122; rdataMC2[1] = 0x2233; rdataMC2[2] = 0x3344; rdataMC2[3] = 0x4455; rdataMC2[4] = 0x5566; rdataMC2[5] = 0x6677; rdataMC2[6] = 0x7788; rdataMC2[7] = 0x8899; rdata_point = 0; while(1) { for(i=0;i<8;i++) { McbspaRegs.DXR1.all=rdataMC2[i]; SpiaRegs.SPITXBUF= sdata[i]; while(McbspaRegs.MFFRX.bit.RXFFST ==0 ) { } // Check for receive rdataMC1[i] = McbspaRegs.DRR1.all; rdata[i] = SpiaRegs.SPIRXBUF; } } } // Some Useful local functions void error(void) { // asm(" ESTOP0"); // test failed!! Stop! // for (;;); } void init_mcbsp_spi() { McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word, Digital loopback dis. McbspaRegs.SPCR1.bit.DLB = 0; McbspaRegs.SPCR1.bit.CLKSTP = 2; // Together with CLKXP/CLKRP determines clocking scheme McbspaRegs.PCR.bit.CLKXP = 0; // �����ط������ݣ�CPOL = 0, CPHA = 0 rising edge no delay McbspaRegs.PCR.bit.CLKRP = 0; //�½��ؽ������� McbspaRegs.PCR.bit.CLKXM =0 ; //MCLKXAΪoutput McbspaRegs.XCR2.bit.XPHASE=0; McbspaRegs.RCR2.bit.RPHASE=0; // McbspaRegs.RCR2.bit.RDATDLY=0; // FSX setup time 1 in master mode. 0 for slave mode (Receive) McbspaRegs.XCR2.bit.XDATDLY=0; // FSX setup time 1 in master mode. 0 for slave mode (Transmit) McbspaRegs.RCR1.bit.RFRLEN1=0; McbspaRegs.XCR1.bit.XFRLEN1=0; McbspaRegs.RCR1.bit.RWDLEN1=2; // 16-bit word McbspaRegs.XCR1.bit.XWDLEN1=2; // 16-bit word McbspaRegs.SRGR2.bit.CLKSM=1; McbspaRegs.PCR.bit.SCLKME=0; McbspaRegs.SRGR1.bit.CLKGDV=0x1; //CLKG frequency = (Input clock frequency)/ (CLKGDV + 1) McbspaRegs.PCR.bit.FSXM=0; McbspaRegs.PCR.bit.FSXP=1; McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator delay_loop(); // Wait at least 2 SRG clock cycles McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset } void mcbsp_fifo_init() { McbspaRegs.MFFTX.all=0x000F; McbspaRegs.MFFRX.all=0x001F; McbspaRegs.MFFCT.all=0x0; McbspaRegs.MFFINT.all=0x0; McbspaRegs.MFFST.all=0x0; McbspaRegs.MFFTX.bit.MFFENA=1; // Enable FIFO McbspaRegs.MFFTX.bit.TXFIFO_RESET=1; // Enable Transmit channel McbspaRegs.MFFRX.bit.RXFIFO_RESET=1; // Enable Receive channel } void spi_fifo_init() { // Initialize SPI FIFO registers SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI SpiaRegs.SPICCR.all=0x000F; //16-bit character, Loopback mode����Ϊ0 SpiaRegs.SPICTL.all=0x0017; //Interrupt enabled, Master XMIT enabled����λΪ0����ģʽ SpiaRegs.SPISTS.all=0x0000; SpiaRegs.SPIBRR=0x0063; // Baud rateΪLSP/100��������375KHZ SpiaRegs.SPIFFTX.all=0xC028; // Enable FIFO's, set TX FIFO level to 8 SpiaRegs.SPIFFRX.all=0x0028; // Set RX FIFO level to 8 SpiaRegs.SPIFFCT.all=0x00; SpiaRegs.SPIPRI.all=0x0010; SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SPI SpiaRegs.SPIFFTX.bit.TXFIFO=1; SpiaRegs.SPIFFRX.bit.RXFIFORESET=1; } //=========================================================================== // No more. //===========================================================================