EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO16 (SPISIMOA)
GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO17 (SPISOMIA)
GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO18 (***)
GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO18 (***)
// GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pull-up on GPIO19 (SPISTEA)
// GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA)
// GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA)
// GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (***)
// GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO57 (SPISTEA)
/* Set qualification for selected pins to asynch only */
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (***)
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO18 (***)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO19 (SPISTEA)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (***)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA)
/* Configure SPI-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be SPI functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO16 as SPISIMOA
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO17 as SPISOMIA
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO18 as ***
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO18 as ***
// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0; // Configure GPIO16 as SPISIMOA
// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 0; // Configure GPIO17 as SPISOMIA
// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0; // Configure GPIO18 as ***
// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // Configure GPIO18 as ***
// GpioCtrlRegs.GPBMUX2.bit.GPIO61 =0; // Configure GPIO19 as SPISTEA
// GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA
// GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA
// GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as ***
// GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA
// GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1; // All outputs
EDIS;
