我想使用ePWM4的A和B作为同步整流驱动信号，仿真二极管的模式，实际调试发现ePWM4A只有A路正常，B路自动变成了互补发波。我的想法是在周期为0时A路导通，向上计数达到COMPA时停止，PWM周期的中点让B路导通，在向下计数达到COMPB时关闭B路。感觉可能是DB模块设置的有问题，请各位大神看下
void EPWMInit(void)
{
EALLOW;
//50k 60M/50K=1200
EPwm1Regs.TBPRD = 1200;
//不相移，计数器与时钟信号同步
EPwm1Regs.TBPHS.half.TBPHS = 0;
//采用向上计数模式；
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
//相移关闭；
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
// 使用镜像寄存器,不直接操作TBPRD寄存器
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
// CTR = ZERO 时，发出同步时钟，
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
//EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
// TBCLK时钟分频； TBCLK = SYSCLKOUT/(CLKDIV * HSPCLKDIV),CLKDIV = 1;
EPwm1Regs.TBCTL.bit.CLKDIV=TB_DIV1;
// HSPCLKDIV = 1; TBCLK = SYSCLKOUT(60Mhz);
EPwm1Regs.TBCTL.bit.HSPCLKDIV=TB_DIV1;
// CMPA寄存器使用镜像模式；
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
// CMPB寄存器使用镜像模式；
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
// 当CTR = 周期值 时，将CMPA镜像中的数据加载到CMPA执行寄存器中；
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
// 当CTR = 周期值 时，将CMPB镜像中的数据加载到CMPB执行寄存器中；
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD;
// 当CTR = 0,EPWM1A = 1;
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
// 当CTR = CMPA,EPWM1A = 0;
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
// enable Dead-band module DBA_ALL
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
// 上升沿延迟器输出端口不翻转，下升沿延迟器输出端口翻转；
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
//死区8*1/60MHz 16.67ns×8
EPwm1Regs.DBFED = 8;
//死区8*1/60MHz
EPwm1Regs.DBRED = 8;
EPwm1Regs.CMPA.half.CMPA=600;
//50k 60M/50K=1200
EPwm2Regs.TBPRD = 1200;
//不相移，计数器与时钟信号同步
EPwm2Regs.TBPHS.half.TBPHS = 0;
//采用向上计数模式；
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
//slave 功能
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
// Count DOWN on sync (=90 deg)
EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN;
// 使用镜像寄存器,不直接操作TBPRD寄存器
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
//ync flow-through
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
// TBCLK时钟分频； TBCLK = SYSCLKOUT/(CLKDIV * HSPCLKDIV),CLKDIV = 1;
EPwm2Regs.TBCTL.bit.CLKDIV=TB_DIV1;
// HSPCLKDIV = 1; TBCLK = SYSCLKOUT(60Mhz);
EPwm2Regs.TBCTL.bit.HSPCLKDIV=TB_DIV1;
// CMPA寄存器使用镜像模式；
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
// CMPB寄存器使用镜像模式；
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
// 当CTR = 0 时，将CMPA镜像中的数据加载到CMPA执行寄存器中；
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
// 当CTR = 0 时，将CMPB镜像中的数据加载到CMPA执行寄存器中；
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// 当CTR=CMPA是置高，CTR=CMPB时拉低
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm2Regs.AQCTLA.bit.CBU = AQ_CLEAR;
// enable Dead-band module DBA_ALL
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
// 上升沿延迟器输出端口不翻转，下升沿延迟器输出端口翻转；
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
//死区8*1/60MHz
EPwm2Regs.DBFED = 8;
//死区8*1/60MHz
EPwm2Regs.DBRED = 8;
EPwm2Regs.CMPA.half.CMPA=600;
//50k 60M/50K=1200
EPwm4Regs.TBPRD = 600;
//不相移，计数器与时钟信号同步
EPwm4Regs.TBPHS.half.TBPHS = 0;
//采用向上计数模式；
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
//slave 功能
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;
// Count DOWN on sync (=90 deg)
//EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN;
// 使用镜像寄存器,不直接操作TBPRD寄存器
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
//ync flow-through
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
// TBCLK时钟分频； TBCLK = SYSCLKOUT/(CLKDIV * HSPCLKDIV),CLKDIV = 1;
EPwm4Regs.TBCTL.bit.CLKDIV=TB_DIV1;
// HSPCLKDIV = 1; TBCLK = SYSCLKOUT(60Mhz);
EPwm4Regs.TBCTL.bit.HSPCLKDIV=TB_DIV1;
// CMPA寄存器使用镜像模式；
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
// CMPB寄存器使用镜像模式；
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
// 当CTR = 0 时，将CMPA镜像中的数据加载到CMPA执行寄存器中；
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
// 当CTR = 0 时，将CMPB镜像中的数据加载到CMPA执行寄存器中；
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// 当CTR=CMPA是置高，CTR=CMPB时拉低
EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm4Regs.AQCTLB.bit.PRD = AQ_SET;
EPwm4Regs.AQCTLB.bit.CBD = AQ_CLEAR;
// enable Dead-band module DBA_ALL
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
// 上升沿延迟器输出端口不翻转，下升沿延迟器输出端口翻转；
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
//死区8*1/60MHz
EPwm4Regs.DBFED = 8;
//死区8*1/60MHz
EPwm4Regs.DBRED = 8;
EPwm4Regs.CMPA.half.CMPA=600;
//TZ1 will be one shot signal for EPWM1
EPwm1Regs.TZSEL.bit.OSHT1=TZ_ENABLE;
EPwm2Regs.TZSEL.bit.OSHT1=TZ_ENABLE;
//EPwm4Regs.TZSEL.bit.OSHT1=TZ_ENABLE;
//TZ will Force EPWM1A to a low state
EPwm1Regs.TZCTL.bit.TZA=TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.TZA=TZ_FORCE_LO;
//EPwm4Regs.TZCTL.bit.TZA=TZ_FORCE_LO;
//TZ will Force EPWM1B to a low state
EPwm1Regs.TZCTL.bit.TZB=TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.TZB=TZ_FORCE_LO;
//EPwm4Regs.TZCTL.bit.TZB=TZ_FORCE_LO;
// TZ中断标志位全部清0；
EPwm1Regs.TZCLR.all = 0xffff;
// 中断均不使能；
EPwm1Regs.TZEINT.all = 0;
// 数值比较器暂不适用；
EPwm1Regs.TZDCSEL.all = 0;
// TZ中断标志位全部清0；
EPwm2Regs.TZCLR.all = 0xffff;
// 中断均不使能；
EPwm2Regs.TZEINT.all = 0;
// 数值比较器暂不适用；
EPwm2Regs.TZDCSEL.all = 0;
// TZ中断标志位全部清0；
EPwm4Regs.TZCLR.all = 0xffff;
// 中断均不使能；
EPwm4Regs.TZEINT.all = 0;
// 数值比较器暂不适用；
EPwm4Regs.TZDCSEL.all = 0;
EDIS;
1和4是对角管子，2，3是epwm4的A和B路
