TMS320F280039: CLB模块延时问题

Han Meng

Part Number: TMS320F280039

Hi Experts:

我们在应用中使用了CLB模块，目的是将EPWM8B通过CLB配置到特定IO脚上，该IO脚本身不能配置为epwm口。配置如下：将EPWM8B AQ模块的输出作为 CLB_IN4的输入,并通过CLBoutputxbar将CLB output6的输出配置到IO引脚上，实测发现经过CLB模块后的驱动波形相对于原始的epwm8B模块存在固定延时（23ns左右），我们的应用中对延时比较模块，请问有什么办法解决吗？谢谢！

10 个月前

0 Ben Qin 10 个月前

TI__Mastermind 39885 points

你好，我咨询相关资深工程师后回复您。

0 Ben Qin 10 个月前

TI__Mastermind 39885 points

你好，参考下工程师的回复：

It looks like you have the input synchronization enabled, this itself adds 2-3 clock cycles delay to whatever input is coming in (which is approximately the delay you're seeing). Keep in mind that this is normally required if you're doing any synchronized logic (i.e. comparing timer values, etc.) with an unsynchronized signal like the ePWM. If you are just simply routing the signal through the CLB to be able to route it to a certain GPIO pin, you can disable this.