This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
void initmcbsp() { //*************** RESET MCBSP McbspaRegs.SPCR2.bit.GRST =0; McbspaRegs.SPCR2.bit.FRST=0; McbspaRegs.SPCR1.bit.RRST=0; McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word McbspaRegs.SPCR1.bit.DLB = 0; McbspaRegs.SPCR1.bit.RRDY=0; McbspaRegs.PCR.bit.FSRM=10; McbspaRegs.MFFINT.all=0x0; //// Disable all interrupts McbspaRegs.RCR2.all=0x0000; // Single-phase frame, 1 word/frame, No companding (Receive) McbspaRegs.RCR1.all=0x0000; //*************** Initialize McBSP Registers // McBSP register settings for Digital loop back McbspaRegs.RCR2.all=0x0001; // RDATDLY = 1 McbspaRegs.RCR1.all=0x0; McbspaRegs.XCR2.all=0x0001; // XDATDLY = 1 McbspaRegs.XCR1.all=0x0; McbspaRegs.SRGR2.all=0x3140; McbspaRegs.SRGR1.all=0x010f; McbspaRegs.MCR2.all=0x0; McbspaRegs.MCR1.all=0x0; McbspaRegs.PCR.all=0x0A00; McbspaRegs.MFFINT.bit.XINT = 0; // Enable Transmit Interrupts McbspaRegs.MFFINT.bit.RINT = 1; McbspaRegs.RCR1.all=0x0000; McbspaRegs.RCR2.all=0x0000; McbspaRegs.SRGR1.all=0x0000; McbspaRegs.SRGR2.all=0x0000; McbspaRegs.PCR.all=0x0000; //开始设置mcbsp// //设置mcbsp时钟生成器,并通过硬件仿真进行观察// //停止模式设置成0// //lspclk=4,clkgdv=63使得CLKG=314khz// McbspaRegs.SPCR1.bit.CLKSTP=00; McbspaRegs.PCR.bit.SCLKME=0; McbspaRegs.SRGR2.bit.CLKSM=1; McbspaRegs.SRGR1.bit.CLKGDV=3; McbspaRegs.SPCR1.bit.DLB=0; McbspaRegs.SPCR1.bit.RJUST=01; McbspaRegs.SPCR1.bit.RINTM=01; McbspaRegs.PCR.bit.CLKRM=1; McbspaRegs.MCR1.bit.RMCM=0; McbspaRegs.SRGR2.bit.FPER=63; McbspaRegs.SRGR2.bit.GSYNC=0; McbspaRegs.PCR.bit.FSRM=1; McbspaRegs.SRGR1.bit.FWID=31; ////////////////////////////// ///////////////////////////// ///////////////////////////// McbspaRegs.RCR1.bit.RFRLEN1=0; McbspaRegs.RCR2.bit.RFRLEN2=0; McbspaRegs.RCR1.bit.RWDLEN1=101; McbspaRegs.RCR2.bit.RWDLEN2=101; McbspaRegs.RCR2.bit.RPHASE=1; McbspaRegs.RCR2.bit.RDATDLY=1; McbspaRegs.RCR2.bit.RFIG=1; McbspaRegs.RCR2.bit.RCOMPAND=00; McbspaRegs.PCR.bit.FSRP=1; McbspaRegs.PCR.bit.CLKRP=0; McbspaRegs.MCR1.bit.RMCME=0; McbspaRegs.MCR1.bit.RMCM=0; McbspaRegs.MFFINT.bit.RINT=1; McbspaRegs.SPCR1.bit.RRST=1; McbspaRegs.SPCR2.bit.GRST=1; McbspaRegs.SPCR2.bit.FRST=1; //************* Enable Sample rate generator asm (" NOP "); // Wait at least 2 SRG clock cycles asm (" NOP "); asm (" NOP "); asm (" NOP "); // Wait at least 2 SRG clock cycles asm (" NOP "); EDIS;