TMS320F28388D: 在TMS320F28388D上实现IPC,并将接收到的数据发送到串口助手

//
// Included Files
//
#include "driverlib.h"
#include "device.h"
#include "ipc.h"
//
// Defines
//
#define IPC_CMD_READ_MEM   0x1001
#define IPC_CMD_RESP       0x2001

#define TEST_PASS          0x5555
#define TEST_FAIL          0xAAAA


#pragma DATA_SECTION(readData, "MSGRAM_CPU2_TO_CPU1")        //
//char sdData[170]={'#',',',1,',',2,',',3,',',4,',',5,',',6,'*'};
//char sdData[170]={'#',11,0,3,5,77,36,152,0};
char sdData[17]={1,2,3,4,5,6,7,8,'\n'};
uint32_t  readData[17]={0};
char send_flag=0;

uint32_t pass;                                                                                    //


//
// Main
//
void main(void)
{
    int i;
    //
    // Initialize device clock and peripherals
    //
    Device_init();

    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    //
    // Clear any IPC flags if set already
    //
    //IPC_clearFlagLtoR(IPC_CPU2_L_CPU1_R, IPC_FLAG_ALL);

    IPC_clearFlagLtoR(IPC_CPU2_L_CPU1_R, IPC_FLAG_ALL);                           ////
    //
    // Enable IPC interrupts
    //
   // IPC_registerInterrupt(IPC_CPU2_L_CPU1_R, IPC_INT0, IPC_ISR0);

    // Synchronize both the cores.
        //
        IPC_sync(IPC_CPU2_L_CPU1_R, IPC_FLAG31);

        for(i=0; i<17; i++)
        {
            readData[i] = sdData[i];
        }
        send_flag=1;

    while(1)
    {
        if(send_flag)
        {

                //
                // Send a message without message queue
                // Length of the data to be read is passed as data.
                //
                IPC_sendCommand(IPC_CPU2_L_CPU1_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
                                IPC_CMD_READ_MEM, (uint32_t)readData, 17);                                               ///数据长度

                //
                // Wait for acknowledgment
                //
                IPC_waitForAck(IPC_CPU2_L_CPU1_R, IPC_FLAG0);

                //
                // Read response
                //
                if(IPC_getResponse(IPC_CPU2_L_CPU1_R) == TEST_PASS)
                {
                    pass = 1;
                }
                else
                {
                    pass = 0;
                }
        }
    }

}

//
// Included Files
//
#include "driverlib.h"
#include "device.h"
//
// Defines
//
#define IPC_CMD_READ_MEM   0x1001
#define IPC_CMD_RESP       0x2001

#define TEST_PASS          0x5555
#define TEST_FAIL          0xAAAA


//Define variables                                       ////
//
char CPU2_flag=0;
char start_flag = 0;
char start_cnt = 0;
uint32_t recbuf[17]={0};
char recbuf1[17]={0};

//
// Function prototypes
//
__interrupt void IPC_ISR0();                     ////

//
// Main
//
void main(void)
{
    int t = 0;

    //
    // Initialize device clock and peripherals
    //
    Device_init();


    //
    // Boot CPU2 core
    //
#ifdef _FLASH
    Device_bootCPU2(BOOTMODE_BOOT_TO_FLASH_SECTOR0);
#else
    Device_bootCPU2(BOOTMODE_BOOT_TO_M0RAM);
#endif

    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    //
    // Clear any IPC flags if set already
    //
    IPC_clearFlagLtoR(IPC_CPU1_L_CPU2_R, IPC_FLAG_ALL);

    IPC_registerInterrupt(IPC_CPU1_L_CPU2_R, IPC_INT0, IPC_ISR0);

    //
    // Synchronize both the cores.
    //
    IPC_sync(IPC_CPU1_L_CPU2_R, IPC_FLAG31);

    //Configure SCIB&SCIC
    //
    SCI_setConfig(SCIB_BASE, DEVICE_LSPCLK_FREQ, 256000, (SCI_CONFIG_WLEN_8 | SCI_CONFIG_STOP_ONE | SCI_CONFIG_PAR_NONE));
    SCI_resetChannels(SCIB_BASE);
    SCI_enableModule(SCIB_BASE);
    SCI_performSoftwareReset(SCIB_BASE);
    SCI_setConfig(SCIC_BASE, DEVICE_LSPCLK_FREQ, 230400, (SCI_CONFIG_WLEN_8 | SCI_CONFIG_STOP_ONE | SCI_CONFIG_PAR_NONE));
    SCI_resetChannels(SCIC_BASE);
    SCI_enableModule(SCIC_BASE);
    SCI_performSoftwareReset(SCIC_BASE);

    //
    // Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
    //
    EINT;
    ERTM;

        //
            // Loop forever. Wait for IPC interrupt
            //
    while(1)
    {
        if(CPU2_flag)
        {
            CPU2_flag = 0;
            for(t=0;t<17;t++)
            {
                recbuf1[t]=recbuf[t];
                recbuf[t]=0;                                //测试使用
            }
            for(t=0;t<17;t++)
            {
                SCI_writeCharBlockingNonFIFO(SCIB_BASE, recbuf1[t]);                          //会给CPU2_flag赋1
                if(recbuf1[t] == '\n')
                {
                    recbuf1[t] = 0;
                    break;
                }
                recbuf1[t] = 0;
           }

        }
    }


}
__interrupt void IPC_ISR0()
{
    int i=0;
    int count=0;
    uint32_t command, addr, data;
    bool status = false;

    //
    // Read the command
    //
    IPC_readCommand(IPC_CPU1_L_CPU2_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
                    &command, &addr, &data);

    if(command == IPC_CMD_READ_MEM)
    {
        status = true;

        //
        // Read and compare data
        //

        for(i=0; i<data; i++)
        {
            recbuf[i]=*((uint32_t *)addr + i);
            count++;
            if(count == 9)
            {
                CPU2_flag=1;
                count=0;
                break;
            }

        }

    }
            //if(*((uint32_t *)addr + i) != i)
                //status = false;

    //
    // Send response to C28x core
    //
    if(status)
    {
        IPC_sendResponse(IPC_CPU1_L_CPU2_R, TEST_PASS);
    }
    else
    {
        IPC_sendResponse(IPC_CPU1_L_CPU2_R, TEST_FAIL);
    }

    //
    // Acknowledge the flag
    //
    IPC_ackFlagRtoL(IPC_CPU1_L_CPU2_R, IPC_FLAG0);

    //
    // Acknowledge the PIE interrupt.
    //
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
}