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移植的话需要根据上面我发的文件来移植。如果ADC没有差别的话,那么实际情况不一样也可能是一些其他工程里面的移植细节没有注意到而导致的。具体是那一方面我无从得知,需要根据您的工程以及实际情况来分析。
我使用28003X的时候也遇到了这个问题,AD采样在正常的时候会被干扰导致采样相比于实际值有一个下跌,后面发现是PWM动作的时候相应的SOC序列采样会有异常下跌,具体为什么会有这种干扰也不知道原因,之前听人说003X的抗干扰不行,不知道这是不是具体的表现
重新画了板子,现象还是一样,下面是ADC的初始化程序,帮忙看下是否有错误
void InitSetAdc(Uint type)
{
volatile Uint waite;
int trigsel;
trigsel = 5;
//EALLOW;
#define ANALOGSUBSYS_BASE 0x0005D700U
ADC_setVREF(ANALOGSUBSYS_BASE, 0, 0);
//AnalogSubsysRegs.ANAREFCTL.bit.ANAREFSEL = 0; // 内部基准,1.65(0~3.3V)
//AnalogSubsysRegs.ANAREFCTL.bit.ANAREFBSEL = 0;
//AnalogSubsysRegs.ANAREFCTL.bit.ANAREFCSEL = 0;
EALLOW;
AdcaRegs.ADCCTL2.bit.PRESCALE = 0x02;
AdcbRegs.ADCCTL2.bit.PRESCALE = 0x02;
AdccRegs.ADCCTL2.bit.PRESCALE = 0x02;
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; //All analog circuitry inside the core is powered up
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
//============================================================================================
//复位
for(waite = 0;waite<5000;waite++){} //延时
//------------------------------------------------------------------------------------------------
asm(" RPT #28 || NOP"); // 需延时两个ADCCLK;延时28个空周期
//以下开始设置ADC的控制寄存器、转换通道选择寄存器等
AdcaRegs.ADCBURSTCTL.bit.BURSTEN = 0; // SOC Burst Mode Enable
AdcbRegs.ADCBURSTCTL.bit.BURSTEN = 0; // SOC Burst Mode Enable
AdccRegs.ADCBURSTCTL.bit.BURSTEN = 0; // SOC Burst Mode Enable
//AdcaRegs.ADCOFFTRIM.all = 0;
//AdcbRegs.ADCOFFTRIM.all = 0;
//AdccRegs.ADCOFFTRIM.all = 0;
AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 4; // 通道3转换完成产生中断ADCINT1
if (0 == type)
{
AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1; // ADCINT1 is enabled
}
else
{
AdcbRegs.ADCINTSEL1N2.bit.INT1E = 0; // ADCINT1 is disabled
}
AdcbRegs.ADCINTOVFCLR.bit.ADCINT1 = 1;
#define ADC_IW_A2 0x02 // IW A2
#define ADC_AI4_A5 0x05 // AI4 A5
#define ADC_VV_A6 0x06 // VV A6
#define ADC_IU_B2 0x02 // IU B2
#define ADC_VDC_B5 0x05 // VDC B5
#define ADC_AI5_B8 0x08 // AI5 B8
#define ADC_AI6_B9 0x09 // AI6 B9
#define ADC_IV_B11 0x0B // IV B11
#define ADC_UV_C0 0x00 // UV C0
#define ADC_AI1_C2 0x02 // AI1 C2
#define ADC_TD_C3 0x03 // TD C3
#define ADC_WV_C4 0x04 // WV C4
#define ADC_AI2_C5 0x05 // AI2 C5
#define ADC_ACQPS 2
//********************************ePWM1 ADCSOCA触发,
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcaRegs.ADCSOC2CTL.bit.CHSEL = ADC_IW_A2; // 18:15 SOC0 Channel Select
AdcaRegs.ADCSOC0CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
/*
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcaRegs.ADCSOC1CTL.bit.CHSEL = ADC_IW_A2; // 18:15 SOC0 Channel Select
AdcaRegs.ADCSOC1CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcaRegs.ADCSOC2CTL.bit.CHSEL = ADC_IW_A2; // 18:15 SOC0 Channel Select
AdcaRegs.ADCSOC2CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcaRegs.ADCSOC3CTL.bit.CHSEL = ADC_IW_A2; // 18:15 SOC0 Channel Select
AdcaRegs.ADCSOC3CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
*/
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcaRegs.ADCSOC1CTL.bit.CHSEL = ADC_AI4_A5; // 18:15 SOC0 Channel Select
AdcaRegs.ADCSOC1CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcaRegs.ADCSOC0CTL.bit.CHSEL = ADC_VV_A6; // 18:15 SOC0 Channel Select
AdcaRegs.ADCSOC2CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcbRegs.ADCSOC2CTL.bit.CHSEL = ADC_IU_B2; // 18:15 SOC0 Channel Select
AdcbRegs.ADCSOC0CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
/*
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcbRegs.ADCSOC1CTL.bit.CHSEL = ADC_IU_B2; // 18:15 SOC0 Channel Select
AdcbRegs.ADCSOC1CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdcbRegs.ADCSOC2CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcbRegs.ADCSOC2CTL.bit.CHSEL = ADC_IU_B2; // 18:15 SOC0 Channel Select
AdcbRegs.ADCSOC2CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdcbRegs.ADCSOC3CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcbRegs.ADCSOC3CTL.bit.CHSEL = ADC_IU_B2; // 18:15 SOC0 Channel Select
AdcbRegs.ADCSOC3CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
*/
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcbRegs.ADCSOC1CTL.bit.CHSEL = ADC_VDC_B5; // 18:15 SOC0 Channel Select
AdcbRegs.ADCSOC1CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdcbRegs.ADCSOC2CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcbRegs.ADCSOC0CTL.bit.CHSEL = ADC_AI5_B8; // 18:15 SOC0 Channel Select
AdcbRegs.ADCSOC2CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdcbRegs.ADCSOC3CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcbRegs.ADCSOC3CTL.bit.CHSEL = ADC_AI6_B9; // 18:15 SOC0 Channel Select
AdcbRegs.ADCSOC3CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdcbRegs.ADCSOC4CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcbRegs.ADCSOC4CTL.bit.CHSEL = ADC_IV_B11; // 18:15 SOC0 Channel Select
AdcbRegs.ADCSOC4CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdccRegs.ADCSOC0CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdccRegs.ADCSOC0CTL.bit.CHSEL = ADC_UV_C0; // 18:15 SOC0 Channel Select
AdccRegs.ADCSOC0CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdccRegs.ADCSOC1CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdccRegs.ADCSOC1CTL.bit.CHSEL = ADC_AI1_C2; // 18:15 SOC0 Channel Select
AdccRegs.ADCSOC1CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdccRegs.ADCSOC2CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdccRegs.ADCSOC2CTL.bit.CHSEL = ADC_TD_C3; // 18:15 SOC0 Channel Select
AdccRegs.ADCSOC2CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdccRegs.ADCSOC3CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdccRegs.ADCSOC3CTL.bit.CHSEL = ADC_WV_C4; // 18:15 SOC0 Channel Select
AdccRegs.ADCSOC3CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdccRegs.ADCSOC4CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdccRegs.ADCSOC4CTL.bit.CHSEL = ADC_AI2_C5; // 18:15 SOC0 Channel Select
AdccRegs.ADCSOC4CTL.bit.ACQPS = ADC_ACQPS; // 8:0 SOC0 Acquisition Prescale
AdccRegs.ADCSOC5CTL.bit.TRIGSEL = trigsel; //ePWM1, ADCSOCA
AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
EDIS;
}
你有没有注意过你的SOC是在什么时间触发的,有没有和EPWM做同步,如果soc开始的时刻恰好和pwm动作的时刻(开通或者关断)重合,003X的采样是会有异常,这是我观察到的现象
SOC是EPWM上溢和下溢触发的。你说的PWM开通关断影响AD采样是有可能的,因为电机转速低是正常的,电机运行到80%额定转速时就会出现抖动,这时候PWM输出的电压矢量比较大,PWM开通关断是接近于SOC触发点的
目前只用003X这样用了,其他的芯片都是开关频率较低,每个开关周期都触发soc和中断,所以采样和pwm动作是同步的,避开了在动作时触发采样,目前的新工程开关频率较高,而且还使用了变频控制,pwm没有再和采样同步了,所以就发现了这个问题,其他的芯片我没有这么用过
你好,
是否考虑了任何系统时钟差异?F28004x 是 100MHz 器件,而 F28003x 的运行频率高达 120MHz
使用的什么硬件?EVM 还是定制?
除 C2000 芯片外,F28004x 和 F28003x 系统硬件之间是否存在任何差异?
可以通过在开环控制下运行电机并绘制检测数据(电流/电压)来比较和验证其ADC采样性能
可以尝试 F28004x 和 F28003x 系统并进行比较
时钟差异已经考虑到了,28034,28335平台都用过没遇到问题。硬件是自己设计的。目前带的永磁同步电机,没办法纯开环运行电机。上个星期我们平台又切换到小华的448芯片,目前带电机都是正常
参考下工程师的回复:
28034,28335平台都用过没遇到问题
F2803x / F2833x devices are Gen2 devices and the peripherals are quite different compared to F28004x / F28003x devices.
They can review the F28004x to F28003x migration guide below, there may be some important differences they need to account for.