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void Epwm1Init() { EALLOW; //120kHz // Config for conventional PWM first EPwm1Regs. TBCTL.bit.PRDLD = TB_SHADOW; // set TB_SHADOW load EPwm1Regs.TBPRD = 632; // 120M/95K/2 = 632; EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; EPwm1Regs.TBPHS.bit.TBPHS = 0; EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE ; // EPWM1 is the Master EPwm1Regs.TBCTL.bit.PRDLD = 0; EPwm1Regs.TBCTL2.bit.PRDLDSYNC = 1; EPwm1Regs.EPWMSYNCOUTEN.bit.ZEROEN = 1; EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Note: ChB is initialized here only for comparison purposes, it is not required EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // optional EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // optional // EPwm1Regs.AQCTLA.bit.CAD = AQ_SET; // EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; // optional // EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; // optional EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR ; EPwm1Regs.AQCTLA.bit.CAD = AQ_SET ; //配置死区; // EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED; // EPwm1Regs.DBCTL.bit.POLSEL = DBA_ALL; // EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm1Regs.DBCTL.bit.POLSEL = DBA_RED_DBB_FED; EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm1Regs.DBFED.all = 96;//800ns EPwm1Regs.DBRED.all = 96; // HRPWM EPwm1Regs.HRCNFG.all = 0x0; EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; EPwm1Regs.HRCNFG.bit.AUTOCONV = 1; EPwm1Regs.HRPCTL.bit.HRPE = 1; EDIS; } void Epwm2Init() { EALLOW; //120kHz // Config for conventional PWM first EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set TB_SHADOW load EPwm2Regs.TBPRD = 632; // 120M/95K/2 = 632; EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; EPwm2Regs.TBPHS.bit.TBPHS = 0; EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // EPWM1 is the Master EPwm2Regs.TBCTL.bit.PRDLD = 0; EPwm2Regs.TBCTL2.bit.PRDLDSYNC = 1; EPwm2Regs.EPWMSYNCINSEL.bit.SEL = 0x01; EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Note: ChB is initialized here only for comparison purposes, it is not required EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // optional EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // optional EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; EPwm2Regs.AQCTLA.bit.CAD = AQ_SET; //配置死区; EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm2Regs.DBCTL.bit.POLSEL = DBA_RED_DBB_FED; EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm2Regs.DBFED.all = 96;//800ns EPwm2Regs.DBRED.all = 96; // HRPWM EPwm2Regs.HRCNFG.all = 0x0; EPwm2Regs.HRCNFG.bit.EDGMODE = HR_BEP; EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; EPwm2Regs.HRCNFG.bit.AUTOCONV = 1; EPwm2Regs.HRPCTL.bit.HRPE = 1; EDIS; }