设计CLB如下，为了测试，OUT 0直接由OUTLUT_0的IN0(配置为1）输出，测试GPIO0输出电平是低电平（理应输出高电平），附上CLB配置步骤，还请帮忙看是不是遗漏了配置，谢谢！
1.InitPeripheralClocks()里使能CLB时钟：
CpuSysRegs.PCLKCR17.bit.CLB1 = 1;
CpuSysRegs.PCLKCR17.bit.CLB2 = 0;
CpuSysRegs.PCLKCR17.bit.CLB3 = 0;
CpuSysRegs.PCLKCR17.bit.CLB4 = 0;
2.CLB初始化
void initTILE1(void)
{
//uint16_t i;
EALLOW;
//Board_init begin.........................................................
//CLB_init.................................................................
//CLB output en
Clb1LogicCtrlRegs.CLB_OUT_EN = 0xFF;--尝试了0x00,0x0F等配置
Clb1LogicCfgRegs.CLB_MISC_ACCESS_CTRL.bit.BLKEN = 0; //CLB_enableOutputMaskUpdates
// myCLB0 CLB_IN0/1 initialization
//
// The following functions configure the CLB input mux and whether the inputs
// have synchronization or pipeline enabled; check the device manual for more
// information on when a signal needs to be synchronized or go through a
// pipeline filter
//
Clb1LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_0 = 0; //CLB1_GLB_MUX_OUT
Clb1LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_1 = 0; //CLB1_GLB_MUX_OUT
Clb1LogicCtrlRegs.CLB_GLBL_MUX_SEL_1.bit.GLBL_MUX_SEL_IN_0 = 64; //CLB_GLOBAL_IN_MUX_CLB_AUXSIG0
Clb1LogicCtrlRegs.CLB_GLBL_MUX_SEL_1.bit.GLBL_MUX_SEL_IN_1 = 65; //CLB_GLOBAL_IN_MUX_CLB_AUXSIG1
Clb1LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_0 = 0; //Input comes from selected external input
Clb1LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_1 = 0; //Input comes from selected external input
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.SYNC0 = 1; //enable sync for in0
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.SYNC1 = 1; //enable sync for in1
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.FIN0 = 0; //no filter
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.FIN1 = 0; //no filter
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.PIPE0 = 0; //CLB_disableInputPipelineMode
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.PIPE1 = 0; //CLB_disableInputPipelineMode
//CLB_setGPREG
Clb1LogicCtrlRegs.CLB_GP_REG.all = 0;
//CLB_enableCLB
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.GLOBAL_EN = 1;
//CLB_OUTPUTXBAR_init......................................................
ClbOutputXbarRegs.OUTPUTLATCHENABLE.bit.OUTPUT8 = 0; //disable latch
ClbOutputXbarRegs.OUTPUTINV.bit.OUTPUT8 = 0; //don't invert
ClbOutputXbarRegs.OUTPUT8MUX0TO15CFG.bit.MUX0 = 0; // CLB1 out0
ClbOutputXbarRegs.OUTPUT8MUXENABLE.bit.MUX0 = 1;
ClbOutputXbarRegs.OUTPUTLATCHENABLE.bit.OUTPUT7 = 0; //disable latch
ClbOutputXbarRegs.OUTPUTINV.bit.OUTPUT7 = 0; //don't invert
ClbOutputXbarRegs.OUTPUT7MUX0TO15CFG.bit.MUX2 = 0; // CLB1 out2
ClbOutputXbarRegs.OUTPUT7MUXENABLE.bit.MUX2 = 1;
//CLBXBAR_init.............................................................
// AUXSIG0 and AUXSIG1 configure
ClbXbarRegs.AUXSIG0MUX0TO15CFG.bit.MUX6 = 0; //CMPSS4_CTRIPH
ClbXbarRegs.AUXSIG1MUX0TO15CFG.bit.MUX7 = 0; //CMPSS4_CTRIPL
ClbXbarRegs.AUXSIG0MUXENABLE.bit.MUX6 = 1;
ClbXbarRegs.AUXSIG1MUXENABLE.bit.MUX7 = 1;
//Board_init end...........................................................
//
// Disable Pipeline Mode
//
// CLB_disablePipelineMode(base);
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.PIPELINE_EN = 0;
//
// Output LUT
//
//
// Equation for Output Look-Up Table Block 0 for TILE1: i0
//
//CLB_configOutputLUT(base, CLB_OUT0, TILE1_CFG_OUTLUT_0);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN0 = 8; //OUT 0输出1
//
// Equation for Output Look-Up Table Block 1 for TILE1: i0
//
//CLB_configOutputLUT(base, CLB_OUT1, TILE1_CFG_OUTLUT_1);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_1.bit.IN0 = 4; //FSM_0 STATE_BIT_0
//
// Equation for Output Look-Up Table Block 2 for TILE1: i0
//
//CLB_configOutputLUT(base, CLB_OUT2, TILE1_CFG_OUTLUT_2);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.IN0 = 25; //FSM_1 STATE_BIT_0
//
// Equation for Output Look-Up Table Block 3 for TILE1: i0
//
//CLB_configOutputLUT(base, CLB_OUT3, TILE1_CFG_OUTLUT_3);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_3.bit.IN0 = 12; //FSM_1 STATE_BIT_0
//CLB_configOutputLUT(base, CLB_OUT4, TILE1_CFG_OUTLUT_4);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_4.bit.IN0 = 8;
//CLB_configOutputLUT(base, CLB_OUT5, TILE1_CFG_OUTLUT_5);
//CLB_configOutputLUT(base, CLB_OUT6, TILE1_CFG_OUTLUT_6);
//CLB_configOutputLUT(base, CLB_OUT7, TILE1_CFG_OUTLUT_7);
//
// AOC
//
//CLB_configAOC(base, CLB_AOC0, TILE1_OUTPUT_COND_CTR_0);
//CLB_configAOC(base, CLB_AOC1, TILE1_OUTPUT_COND_CTR_1);
//CLB_configAOC(base, CLB_AOC2, TILE1_OUTPUT_COND_CTR_2);
//CLB_configAOC(base, CLB_AOC3, TILE1_OUTPUT_COND_CTR_3);
//CLB_configAOC(base, CLB_AOC4, TILE1_OUTPUT_COND_CTR_4);
//CLB_configAOC(base, CLB_AOC5, TILE1_OUTPUT_COND_CTR_5);
//CLB_configAOC(base, CLB_AOC6, TILE1_OUTPUT_COND_CTR_6);
//CLB_configAOC(base, CLB_AOC7, TILE1_OUTPUT_COND_CTR_7);
//
// LUT 0 - 2 are configured as macros in clb_config.h; these macros are used in
// CLB_selectLUT4Inputs and CLB_configLUT4Function
//
//
// LUT Configuration
//
//CLB_selectLUT4Inputs(base, TILE1_CFG_LUT4_IN0, TILE1_CFG_LUT4_IN1, TILE1_CFG_LUT4_IN2, TILE1_CFG_LUT4_IN3);
//CLB_configLUT4Function(base, TILE1_CFG_LUT4_FN10, TILE1_CFG_LUT4_FN2);
//
// FSM 0 - 2 are configured in <file>
//
// State 0 output equation for Finite State Machine 0 for TILE1: ((~s0)&e0)|(s0&e1)
// User Description for Finite State Machine 0 for TILE1
/*
complementary ePWMA
*/
// State 0 output equation for Finite State Machine 1 for TILE1: ((~s0)&e0)|(s0&(~e1))
// User Description for Finite State Machine 1 for TILE1
/*
complementary ePWMB
*/
//
// FSM
//
//CLB_selectFSMInputs(base, TILE1_CFG_FSM_EXT_IN0, TILE1_CFG_FSM_EXT_IN1, TILE1_CFG_FSM_EXTRA_IN0, TILE1_CFG_FSM_EXTRA_IN1);
//CLB_configFSMNextState(base, TILE1_CFG_FSM_NEXT_STATE_0, TILE1_CFG_FSM_NEXT_STATE_1, TILE1_CFG_FSM_NEXT_STATE_2);
//CLB_configFSMLUTFunction(base, TILE1_CFG_FSM_LUT_FN10, TILE1_CFG_FSM_LUT_FN2);
Clb1LogicCfgRegs.CLB_FSM_EXTERNAL_IN0.all = TILE1_CFG_FSM_EXT_IN0;
Clb1LogicCfgRegs.CLB_FSM_EXTERNAL_IN1.all = TILE1_CFG_FSM_EXT_IN1;
Clb1LogicCfgRegs.CLB_FSM_EXTRA_IN0.all = TILE1_CFG_FSM_EXTRA_IN0;
Clb1LogicCfgRegs.CLB_FSM_EXTRA_IN1.all = TILE1_CFG_FSM_EXTRA_IN1;
Clb1LogicCfgRegs.CLB_FSM_NEXT_STATE_0.all = TILE1_CFG_FSM_NEXT_STATE_0;
Clb1LogicCfgRegs.CLB_FSM_NEXT_STATE_1.all = TILE1_CFG_FSM_NEXT_STATE_1;
Clb1LogicCfgRegs.CLB_FSM_NEXT_STATE_2.all = TILE1_CFG_FSM_NEXT_STATE_2;
Clb1LogicCfgRegs.CLB_FSM_LUT_FN1_0.all = TILE1_CFG_FSM_LUT_FN10;
Clb1LogicCfgRegs.CLB_FSM_LUT_FN2.all = TILE1_CFG_FSM_LUT_FN2;
//
// Counter 0 - 2 are configured in <file>
//
// User Description for Counter 0 for TILE1
/*
reset counter with input 0(CMPSS4 TRIPH) and load with input 1(CMPSS4 TRIP-
L)
*/
// User Description for Counter 1 for TILE1
/*
PWMA
*/
// User Description for Counter 2 for TILE1
/*
PWMB
*/
//
// Counters
//
//CLB_selectCounterInputs(base, TILE1_CFG_COUNTER_RESET, TILE1_CFG_COUNTER_EVENT, TILE1_CFG_COUNTER_MODE_0, TILE1_CFG_COUNTER_MODE_1);
//CLB_configMiscCtrlModes(base, TILE1_CFG_MISC_CONTROL);
//CLB_configCounterLoadMatch(base, CLB_CTR0, TILE1_COUNTER_0_LOAD_VAL, TILE1_COUNTER_0_MATCH1_VAL, TILE1_COUNTER_0_MATCH2_VAL);
//CLB_configCounterLoadMatch(base, CLB_CTR1, TILE1_COUNTER_1_LOAD_VAL, TILE1_COUNTER_1_MATCH1_VAL, TILE1_COUNTER_1_MATCH2_VAL);
//CLB_configCounterLoadMatch(base, CLB_CTR2, TILE1_COUNTER_2_LOAD_VAL, TILE1_COUNTER_2_MATCH1_VAL, TILE1_COUNTER_2_MATCH2_VAL);
//CLB_configCounterTapSelects(base, TILE1_CFG_TAP_SEL);
Clb1LogicCfgRegs.CLB_COUNT_RESET.all = TILE1_CFG_COUNTER_RESET;
Clb1LogicCfgRegs.CLB_COUNT_EVENT.all = TILE1_CFG_COUNTER_EVENT;
Clb1LogicCfgRegs.CLB_COUNT_MODE_0.all = TILE1_CFG_COUNTER_MODE_0;
Clb1LogicCfgRegs.CLB_COUNT_MODE_1.all = TILE1_CFG_COUNTER_MODE_1;
Clb1LogicCfgRegs.CLB_MISC_CONTROL.all = TILE1_CFG_MISC_CONTROL;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_0_LOAD;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_0_LOAD_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_0_MATCH1;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_0_MATCH1_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_0_MATCH2;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_0_MATCH2_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_1_LOAD;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_1_LOAD_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_1_MATCH1;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_1_MATCH1_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_1_MATCH2;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_1_MATCH2_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_2_LOAD;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_2_LOAD_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_2_MATCH1;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_2_MATCH1_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_2_MATCH2;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_2_MATCH2_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
//CMPSS output to GPIO for test if CMPSS works well
OutputXbarRegs.OUTPUT1MUX0TO15CFG.bit.MUX6 = 0; //CMPSS4_CTRIPOUTH
OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX6 = 1;
OutputXbarRegs.OUTPUT2MUX0TO15CFG.bit.MUX7 = 0; //CMPSS4_CTRIPOUTL
OutputXbarRegs.OUTPUT2MUXENABLE.bit.MUX7 = 1;
//
// HLC is configured in <file>
//
//
// HLC
//
//CLB_configHLCEventSelect(base, TILE1_HLC_EVENT_SEL);
//CLB_setHLCRegisters(base, TILE1_HLC_R0_INIT, TILE1_HLC_R1_INIT, TILE1_HLC_R2_INIT, TILE1_HLC_R3_INIT);
//for(i = 0; i <= CLB_NUM_HLC_INSTR; i++)
//{
// CLB_programHLCInstruction(base, i, TILE1HLCInstr[i]);
//}
EDIS;
}
3.GPIO MUX
EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 2;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 3; // Configure GPIO0 as CLB output
GpioCtrlRegs.GPAGMUX1.bit.GPIO1 = 2;
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3; // Configure GPIO1 as CLB output
EDIS;
