现工程须要通过GPIO模拟SPI时序,通过测试发现采用Timer控制时序的话,所能达到的最小周期在0.5μs,用DSP/BIOS的话在10μs左右,现有几个疑惑请教一下:
1. 跳转中断服务程序的开销是否每次都一样,与程序当前运行环境无关
2. DSP/BIOS的HWI硬件中断的跳转开销是否比普通工程更多
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