那位了解的过来帮我分析一下，谢谢了！

我想使用我板子（F28335）上面的xintf模块zone0区，但是我配置完成后，测试zone0区的XZCS信号一直都是高电平，也就是说它没被选中，这是我程序配置的问题，还是板子的问题，请了解的过来指导一下，谢谢了。我的代码如下：

#define CH375Cmd *(volatile UINT32*)(0x4001) /*总线方式*/
#define CH375Dat *(volatile UINT32*)(0x4000)

void init_zone0(void)
{

SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;

// Configure the GPIO for XINTF with a 16-bit data bus
// This function is in DSP2833x_Xintf.c
InitXintf16Gpio();

EALLOW;
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = SYSCLKOUT
XintfRegs.XINTCNF2.bit.XTIMCLK = 0; //XTIMCLK = SYSCLKOUT/1
// Buffer up to 3 writes
XintfRegs.XINTCNF2.bit.WRBUFF = 0; //三个writing buffer
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0; //使能XCLKOUT
// XCLKOUT = XTIMCLK
XintfRegs.XINTCNF2.bit.CLKMODE = 0;//XCLKOUT is equal to XTIMCLK

XintfRegs.XBANK.bit.BCYC = 0; // Add 7 cycles
XintfRegs.XBANK.bit.BANK = 0; // select zone 0

// Zone 0------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING0.bit.XWRLEAD = 2;
XintfRegs.XTIMING0.bit.XWRACTIVE = 4;
XintfRegs.XTIMING0.bit.XWRTRAIL = 2;
// Zone read timing
XintfRegs.XTIMING0.bit.XRDLEAD = 2;
XintfRegs.XTIMING0.bit.XRDACTIVE = 4;
XintfRegs.XTIMING0.bit.XRDTRAIL =2;

// don't double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.X2TIMING = 0;

// Zone will not sample XREADY signal
XintfRegs.XTIMING0.bit.USEREADY = 0;
XintfRegs.XTIMING0.bit.READYMODE = 0;

// 1,1 = x16 data bus
// 0,1 = x32 data bus
// other values are reserved
XintfRegs.XTIMING0.bit.XSIZE = 3;
EDIS;

//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
}

int main(void)
{
InitSysCtrl();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
init_zone0();
CH375Dat = 0x12;
mDelaymS(100 ); /* 延时50ms */

return 0;
}