3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK) Each CPU provides a clock (CPU1.SYSCLK and CPU2.SYSCLK) to the CLA, DMA, and most owned peripherals. This clock is identical to PLLSYSCLK, but is gated when the CPU enters STANDBY mode. Each peripheral clock can be connected to either CPU1.SYSCLK or CPU2.SYSCLK. This selection is made by CPU1 using the CPUSELx registers. Each peripheral clock also has an independent clock gating that is controlled by the CPU PCLKCRx registers. By default, the ePWM and EMIF1 clocks each have an additional /2 divider, which is required to support CPU frequencies over 100MHz. At slower CPU frequencies, these dividers can be disabled using the PERCLKDIVSEL register.
