当配置完CPU2 的Cla初始化函数之后 ， CPU1 的IPC通讯函数卡死
CPU2 IPC配置函数
int counter = 0;
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.IPC0_INT = &CPU01toCPU02IPC0IntHandler;
PieVectTable.IPC1_INT = &CPU01toCPU02IPC1IntHandler;
EDIS; // This is needed to disable write to EALLOW protected registers
IPCInitialize(&g_sIpcController1, IPC_INT0, IPC_INT0);
IPCInitialize(&g_sIpcController2, IPC_INT1, IPC_INT1);
IER |= M_INT1;
PieCtrlRegs.PIEIER1.bit.INTx13 = 1; // CPU1 to CPU2 INT0
PieCtrlRegs.PIEIER1.bit.INTx14 = 1; // CPU1 to CPU2 INT1
ErrorFlag = 0;
FnCallStatus = 0;
usWWord16 = 0;
ulWWord32 = 0;
for(counter = 0; counter < 256; counter++)
{
usCPU02Buffer[counter] = 0;
}
//
// Point array to address in CPU02 TO CPU01 MSGRAM for passing
// variable locations
//
pulMsgRam = (void *)CPU02TOCPU01_PASSMSG;
//
// Write addresses of variables where words should be written to pulMsgRam
// array.
// 0 = Address of 16-bit word to write to.
// 1 = Address of 32-bit word to write to.
// 2 = Address of buffer to block write to.
// 3 = Address of FunctionCall() function to call.
// 4 = Address of FunctionCallParam() function to call.
// 5 = Address of 32-bit FnCallStatus variable to check function call
// executed
//
pulMsgRam[0] = (uint32_t)&usWWord16;
pulMsgRam[1] = (uint32_t)&ulWWord32;
pulMsgRam[2] = (uint32_t)&usCPU02Buffer[0];
pulMsgRam[3] = (uint32_t)&FunctionCall;
pulMsgRam[4] = (uint32_t)&FunctionCallParam;
pulMsgRam[5] = (uint32_t)&FnCallStatus;
//CPU2 CLa 配置函数
//CLA_initCpuXCla1();
DrvClaMemInit();
//
// Compute all CLA task vectors
// On Type-1 CLAs the MVECT registers accept full 16-bit task addresses as
// opposed to offsets used on older Type-0 CLAs
//
EALLOW;
Cla1Regs.MVECT1 = (uint16_t)(&Cla1Task1);
Cla1Regs.MVECT2 = (uint16_t)(&Cla1Task2);
Cla1Regs.MVECT3 = (uint16_t)(&Cla1Task3);
Cla1Regs.MVECT4 = (uint16_t)(&Cla1Task4);
Cla1Regs.MVECT5 = (uint16_t)(&Cla1Task5);
Cla1Regs.MVECT6 = (uint16_t)(&Cla1Task6);
Cla1Regs.MVECT7 = (uint16_t)(&Cla1Task7);
Cla1Regs.MVECT8 = (uint16_t)(&Cla1Task8);
//
// Enable the IACK instruction to start a task on CLA in software
// for all 8 CLA tasks. Also, globally enable all 8 tasks (or a
// subset of tasks) by writing to their respective bits in the
// MIER register
//
Cla1Regs.MCTL.bit.IACKE = 1;
Cla1Regs.MIER.all = (M_INT8 | M_INT7);
//
// Configure the vectors for the end-of-task interrupt for all
// 8 tasks
//
PieVectTable.CLA1_1_INT = &cla1Isr1;
PieVectTable.CLA1_2_INT = &cla1Isr2;
PieVectTable.CLA1_3_INT = &cla1Isr3;
PieVectTable.CLA1_4_INT = &cla1Isr4;
PieVectTable.CLA1_5_INT = &cla1Isr5;
PieVectTable.CLA1_6_INT = &cla1Isr6;
PieVectTable.CLA1_7_INT = &cla1Isr7;
PieVectTable.CLA1_8_INT = &cla1Isr8;
//
// Set the adca.1 as the trigger for task 7
//
//DmaClaSrcSelRegs.CLA1TASKSRCSEL2.bit.TASK7 = 2;
//
// Enable CLA interrupts at the group and subgroup levels
//
PieCtrlRegs.PIEIER11.all = 0xFFFF;
IER |= (M_INT11 );
EDIS;
