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1.clllc,做同步整流;
pwm1、pwm2为原边驱动,pwm6、pwm7为副边同步整流驱动(4路驱动配置均为计数模式updown,1A 1B上下管互补),aqctla选择zero/period置高置低输出电平;
2.使用谐振电流送入比较器(高低两个比较器)后,比较器输出通过xbar配置ctriph到trip4上,ctripl到trip5上;pwm6/7的DCALCOMPSEL/DCBLCOMPSEL选择trip4/5。
1.禁用了死区后问题依旧。
2.pwm6/7没有使用cbc trip。
这个是我配置:
Epwm6Regs.AQCTLA.bit.ZRO=AQ_SET;
Epwm6Regs.AQCTLA.bit.PRD=AQ_CLEAR;
Epwm6Regs.DBCTL.bit.OUTSWAP=3;
Epwm7Regs.AQCTLA.bit.ZRO=AQ_SET;
Epwm7Regs.AQCTLA.bit.PRD=AQ_CLEAR;
Epwm7Regs.DBCTL.bit.OUTSWAP=0;
Epwm6Regs.TZCTLDCA.bit.
DCAEVT2D=2;
Epwm6Regs.TZCTLDCB.bit.
DCAEVT2U=2;
Epwm6Regs.TZCTL2.bit.
ETETZ1;
Epwm7Regs.TZCTLDCA.bit.
DCAEVT2U=2;
Epwm7Regs.TZCTLDCB.bit.
DCAEVT2D=2;
Epwm7Regs.TZCTL2.bit.
ETETZ1;