TMS320F28377D: CPU1控制eMIF1的CS3空间与 FPGA异步通讯，CPU2控制eMIF1的CS2空间与AD7616模拟采集芯片通讯，双核同时使用时数据有异常，单核CPU使用时正常

meta flex

Prodigy 10 points

Part Number: TMS320F28377D

eMIF初始化函数如下，请帮忙指出问题，给出解决方案，谢谢！

void InitEMIF(void)

{

EMIF_AsyncTimingParams tParamAsync;

EMIF_SyncConfig sdConfig;

EMIF_SyncTimingParams tParam;

/********************************EMIF1 FOR FPGA************************************************/

// Configure to run EMIF1 on full Rate. (EMIF1CLK = CPU1SYSCLK)

SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_2); // half rate

// Grab EMIF1 For CPU1.

EMIF_selectMaster(EMIF1CONFIG_BASE, EMIF_MASTER_CPU1_NG);//for ad7616

// Disable Access Protection. (CPU_FETCH/CPU_WR/DMA_WR)

EMIF_setAccessProtection(EMIF1CONFIG_BASE, 0x0);

// Commit the configuration related to protection. Till this bit remains

// set, contents of EMIF1ACCPROT0 register can't be changed.

EMIF_commitAccessConfig(EMIF1CONFIG_BASE);

// Lock the configuration so that EMIF1COMMIT register can't be changed

// any more.

EMIF_lockAccessConfig(EMIF1CONFIG_BASE);

// Configure GPIO pins for EMIF1.

setupEMIF1PinmuxAsync16Bit();

// Configures Normal Asynchronous Mode of Operation.

// CS3 selected

EMIF_setAsyncMode(EMIF1_BASE, EMIF_ASYNC_CS3_OFFSET, EMIF_ASYNC_NORMAL_MODE);

EMIF_setAsyncMode(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET, EMIF_ASYNC_NORMAL_MODE);//for ad7616

// Disables Extended Wait Mode.

// CS3 selected

EMIF_disableAsyncExtendedWait(EMIF1_BASE, EMIF_ASYNC_CS3_OFFSET); // 使用

EMIF_disableAsyncExtendedWait(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET);//for ad7616

// Configure EMIF1 Data Bus Width.

// CS3 selected

EMIF_setAsyncDataBusWidth(EMIF1_BASE, EMIF_ASYNC_CS3_OFFSET, EMIF_ASYNC_DATA_WIDTH_16);

EMIF_setAsyncDataBusWidth(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET, EMIF_ASYNC_DATA_WIDTH_16);//for ad7616

// PengXL

// Configure the access timing for CS3 space.

tParamAsync.rSetup = 3; //读设置时间

tParamAsync.rStrobe = 8; //读选通宽度

tParamAsync.rHold = 2; //读保持时间

tParamAsync.turnArnd = 0; //转向时间

tParamAsync.wSetup = 2; //写设置时间

tParamAsync.wStrobe = 3; //写选通宽度

tParamAsync.wHold = 2; //写保持时间

EMIF_setAsyncTimingParams(EMIF1_BASE, EMIF_ASYNC_CS3_OFFSET, &tParamAsync);

// Configure the access timing for CS2 space.

tParamAsync.rSetup = 3;

tParamAsync.rStrobe = 10;

tParamAsync.rHold = 2;

tParamAsync.turnArnd = 4;

tParamAsync.wSetup = 3;

tParamAsync.wStrobe = 6;

tParamAsync.wHold = 2;

EMIF_setAsyncTimingParams(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET, &tParamAsync);//for ad7616

// Adding some delay.

int i;

for(i = 0; i < 123; i++)

{

asm(" NOP");

}

1 个月前

0 Eirwen 1 个月前

TI__Genius 13055 points

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

0 meta flex 1 个月前回复 Eirwen

Prodigy 10 points

#define EMIF_MASTER_CPU1_NG EMIF_CONTROLLER_CPU1_NG

#define EMIF_MASTER_CPU1_G EMIF_CONTROLLER_CPU1_G

#define EMIF_MASTER_CPU2_G EMIF_CONTROLLER_CPU2_G

#define EMIF_MASTER_CPU1_NG2 EMIF_CONTROLLER_CPU1_NG2

另外，请问这四种模式有什么区别？CPU2是否有NG模式？

0 zhisheng xiong 1 个月前回复 meta flex

Prodigy 240 points

哥们儿我也想知道这个，你搞明白了吗？

0 meta flex 1 个月前回复 zhisheng xiong

Prodigy 10 points

用一个CPU控制 CS0、CS2和CS3倒已经测试可性，上述两个CPU访问的方式还是存在问题

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TMS320F28377D: CPU1控制eMIF1的CS3空间与 FPGA异步通讯，CPU2控制eMIF1的CS2空间与AD7616模拟采集芯片通讯，双核同时使用时数据有异常，单核CPU使用时正常