TMS320F280049C: 关于使用SCI模块的FIFO功能

专家您好！

现在在使用TMS320F280049C的SCI模块FIFO功能时，如何实现一个完整数据包的接收？

比如：我的自定义数据包共有24个字节，而寄存器RXFFIL设置为16，当产生接收FIFO中断时，一次就接收16个字节，剩下的8个字节似乎没有收到，我的SCI初始化配置如下：

可以正常工作，但是我如果在串口程序一次发送24个字节，就只能正确收到16个字节。其余的8字节该用什么方式接收呢？我尽量想使用FIFO，这样可以大幅减少CPU中断次数。

//
// SCI_FIFO_Init - Configure SCIB FIFO
//
void SCI_FIFO_Init(void)
{
    Uint16 i;

    GPIO_SetupPinMux(13, GPIO_MUX_CPU1, 6);
    GPIO_SetupPinOptions(13, GPIO_INPUT, GPIO_PUSHPULL);
    GPIO_SetupPinMux(40, GPIO_MUX_CPU1, 9);
    GPIO_SetupPinOptions(40, GPIO_OUTPUT, GPIO_ASYNC);

    EALLOW;  // This is needed to write to EALLOW protected registers
    PieVectTable.SCIB_RX_INT = &SCI_FIFO_Rx_Isr;
    PieVectTable.SCIB_TX_INT = &SCI_FIFO_Tx_Isr;
    EDIS;    // This is needed to disable write to EALLOW protected registers

   ScibRegs.SCICCR.all = 0x0007;      // 1 stop bit,  No loopback
                                      // No parity,8 char bits,
                                      // async mode, idle-line protocol
   ScibRegs.SCICTL1.all = 0x0003;     // enable TX, RX, internal SCICLK,
                                      // Disable RX ERR, SLEEP, TXWAKE
   ScibRegs.SCICTL2.all = 0x0003;
   ScibRegs.SCICTL2.bit.TXINTENA = 1;
   ScibRegs.SCICTL2.bit.RXBKINTENA = 1;
   //ScibRegs.SCIHBAUD.all = 0x0001;
   //ScibRegs.SCILBAUD.all = 0x0044;
   ScibRegs.SCIHBAUD.all = ((uint16_t)SCI_PRD  & 0xFF00U) >> 8U;
   ScibRegs.SCILBAUD.all = (uint16_t)SCI_PRD  & 0x00FFU;
   ScibRegs.SCICCR.bit.LOOPBKENA = 0; // Disable loop back

   ScibRegs.SCIFFTX.all = 0xC030;//1100 0000 0010 0100

   ScibRegs.SCIFFRX.all = 0x0030;//1100 0000 0010 0100
   ScibRegs.SCIFFCT.all = 0x00;

   ScibRegs.SCICTL1.all = 0x0023;     // Relinquish SCI from Reset
   ScibRegs.SCIFFTX.bit.TXFIFORESET = 1;
   ScibRegs.SCIFFRX.bit.RXFIFORESET = 1;

   for(i = 0; i<20; i++)
   {
      RX_BUFFER[i] = i;
   }

   //rdata_pointA = sdataA[0];

    //
    // Enable interrupts required for this example
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block

    PieCtrlRegs.PIEIER9.bit.INTx3 = 1;   // PIE Group 9, INT3 for RX
    //PieCtrlRegs.PIEIER9.bit.INTx4 = 1;   // PIE Group 9, INT4 for TX

    //PieCtrlRegs.PIEIER9.bit.INTx1 = 1;   // PIE Group 9, INT1
    //PieCtrlRegs.PIEIER9.bit.INTx2 = 1;   // PIE Group 9, INT2
    IER |= 0x100;                          // Enable CPU INT
    EINT;
    ERTM;
}