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TMS320F28P650DK: EPG 使用中 信号发生器的一些问题?

Part Number: TMS320F28P650DK

Hi,we are currently working on embedded development based on the TMS320F28P65 chip and have been using the EPG module recently.We encountered some issues during usage and referred to the TMS320F28P65x device errata document but could't find a proper explanation . Therefore,we would like to ask the following questions:

1、In the "TMS320F28P65x Real-Time Microcontrollers" document,Figure 34-2 describes two SIGGEN submodules,but only one set of signal generator register groups is defined in EPG_REGS.Could you clarify how many signal generators are actually implemented inside the chip?

2、In Figure 34-5 ,the relationship between DATATRANIN and DATATRANOUT is described as follows: only when SIGGENx_CTL0,MODE == BIG_BANG,DATATRANOUT[7:0] ==DATATRANIN.However,in Section34.3,the first paragraph states: "The DATATRANOUT0 to DATATRANOUT7 are connected to DATATRANIN0 to DATATRANIN7 when the signal generator is not in BIT_BANG mode. In BIT_BANG mode, DATATRANOUT0 to DATATRANOUT7 are connected to DATATRANIN0, DATATRANIN8, and DATATRANIN16 to DATATRANIN56." This textual description contradicts the graphical description .Could you clarify which is correct?

3、In table 34-2,EPG DATAIN/DATAOUT defines the connection relationships with 64 signals. However, in EPG_MUX_REGS, the EPGMXSEL0 register is responsible for managing DATAIN[0] to DATAIN[31]. Where is the management for DATAIN[32] to DATAIN[63] defined? Or does the chip actually support only 32 signals instead of 64?

These questions are critical for our embedded development .Please provide a clear response .Thank you

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  • 1、In the "TMS320F28P65x Real-Time Microcontrollers" document,Figure 34-2 describes two SIGGEN submodules,but only one set of signal generator register groups is defined in EPG_REGS.Could you clarify how many signal generators are actually implemented inside the chip?

    There are two SIGGEN modules. The documentation for the second register group is missing; this will be addressed in upcoming documentation/software releases. In the meantime, I can give as guidance: SIGGEN1 registers are the same as SIGGEN0, with the offset (address of SIGGEN1_CTL0) starting at 0x40.

    2、In Figure 34-5 ,the relationship between DATATRANIN and DATATRANOUT is described as follows: only when SIGGENx_CTL0,MODE == BIG_BANG,DATATRANOUT[7:0] ==DATATRANIN.However,in Section34.3,the first paragraph states: "The DATATRANOUT0 to DATATRANOUT7 are connected to DATATRANIN0 to DATATRANIN7 when the signal generator is not in BIT_BANG mode. In BIT_BANG mode, DATATRANOUT0 to DATATRANOUT7 are connected to DATATRANIN0, DATATRANIN8, and DATATRANIN16 to DATATRANIN56." This textual description contradicts the graphical description .Could you clarify which is correct?

    The textual description is incorrect. The diagram reflects the correct behavior: DATAIN[7:0] => DATAOUT[7:0] when mode == BITBANG. This will be fixed in the next documentation release.

    3、In table 34-2,EPG DATAIN/DATAOUT defines the connection relationships with 64 signals. However, in EPG_MUX_REGS, the EPGMXSEL0 register is responsible for managing DATAIN[0] to DATAIN[31]. Where is the management for DATAIN[32] to DATAIN[63] defined? Or does the chip actually support only 32 signals instead of 64? These questions are critical for our embedded development .Please provide a clear response .

    There are 64 signals, but the register definition for EPGMXSEL1 (for DATAIN[63:32]) is missing. This register is at address offset 0x2.